Integrated Chip Package Layout for PCB Space Reduction
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Solution Overview
Problem
Existing chip packages with light emitters and receivers require significant space on printed circuit boards, hindering miniaturization and increasing assembly costs due to the inability to be packaged together during manufacturing.
Innovation Solution
A chip package design that integrates a light emitter and a light receiver on the same chip, utilizing a support layer, light transmissive sheets, a redistribution layer, and a conductive structure, allowing for both light emission and reception, and a manufacturing method that uses wafer level packaging to combine these components efficiently.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Reliability
If light emitter and light receiver are packaged separately, then each component can be optimized independently, but the space required on the printed circuit board increases and assembly cost increases
Solution Approach 1:
The patent combines the light emitter and light receiver into a single chip package, integrating multiple light functions (emission and reception) on one chip. This merging eliminates the need for separate packaging of individual components, thereby reducing the space required on the printed circuit board while maintaining component optimization through integrated design
2Ease of manufacture
If light emitter and light receiver are packaged separately, then manufacturing processes can be simplified, but assembly cost increases and production efficiency decreases
Solution Approach 1:
The patent implements wafer-level packaging to combine multiple chips containing light functions into a single package during the wafer fabrication process. This approach enables parallel processing of multiple chips simultaneously, improving production efficiency and reducing assembly costs while maintaining manufacturing process simplicity through standardized wafer-level operations
3Area of stationary object
If multiple light functions are integrated on a single chip, then miniaturization is achieved and assembly cost is reduced, but manufacturing complexity increases
Solution Approach 1:
The patent performs preliminary packaging actions at the wafer level before chip dicing, completing the packaging structure formation while the chips are still connected on the wafer. This preliminary action simplifies subsequent manufacturing steps and reduces overall manufacturing complexity despite the integration of multiple light functions on a single chip package
Applied Scientific Principles
This section explains which scientific principles are used to turn an abstract innovation direction into a practical engineering solution.
Function Achieved in This Case
Facilitates miniaturization and reduces assembly costs by enabling multiple light functions on a single chip package, improving production efficiency and yield.
Implementation Method 1
The first light transmissive sheet is located on the first support layer and covers the first light receiver
Data Source
AI summary
A chip package includes a chip, a first support layer, a light emitter, a first light transmissive sheet, a redistribution layer, and a conductive structure. A top surface of the chip has a conductive pad and a first light receiver. The first support layer is located on the top surface of the chip. The light emitter is located on the top surface of the chip. The first light transmissive sheet is located on the first support layer and covers the first light receiver. The redistribution layer is electrically connected to the conductive pad and extends to a bottom surface of the chip. The conductive structure is located on the redistribution layer that is on the bottom surface of the chip.