Integrated Circuit Resistive Memory String with Shared Source/Drain Regions
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Solution Overview
Problem
Existing resistive memory cell architectures face challenges with increased series resistance and interference during operations like reading or programming/erasing, affecting the efficiency of selected memory cells.
Innovation Solution
A layout is introduced for a resistive memory string with parallel transistors and resistors, allowing for a compact and flexible design that minimizes series resistance by using shared source/drain regions and optimized metal connections, along with an inhibit scheme to maintain non-selected cells undisturbed during operations.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Reliability
If traditional resistive memory cell architectures are used, then memory storage capability is achieved, but series resistance increases and interference occurs during reading or programming/erasing operations
Solution Approach 1:
The memory string is divided into multiple memory cells with individual word line transistors and resistors. Each memory cell is segmented with its own control transistor, allowing selective activation and reducing interference between cells. The shared source/drain regions create distinct segments that can be independently controlled.
Solution Approach 2:
Word line transistors serve as intermediary elements between the control circuitry and the resistive memory elements. These transistors act as switches that control current flow to selected memory cells, preventing interference with non-selected cells and reducing overall series resistance by providing controlled access paths.
2Quantity of substance
If memory density is increased through integration, then more components fit in given area, but series resistance increases and operational efficiency decreases
Solution Approach 1:
Adjacent memory cells share common source/drain regions, merging physical structures to reduce redundancy. This sharing approach decreases the total number of discrete components needed, reducing series resistance while maintaining high integration density. The shared regions create more efficient current paths through the memory string.
Solution Approach 2:
The patent utilizes vertical stacking and three-dimensional arrangement of memory cells, transistors, and interconnect structures. By moving from a purely planar layout to a multi-dimensional structure, more memory cells can be integrated without proportionally increasing series resistance, as current paths are optimized through vertical connections and shared horizontal regions.
3Area of stationary object
If compact memory design is implemented, then area is reduced, but metal connections and layout complexity increase
Solution Approach 1:
Shared source/drain regions serve multiple functions: they act as electrical connections between adjacent memory cells, provide structural support, and function as common terminals for multiple transistors. This multi-functionality reduces the need for separate metal connections, simplifying the interconnect architecture while maintaining compact design.
Solution Approach 2:
Instead of using traditional metal interconnects to connect memory cells, the patent inverts the approach by making the source/drain regions themselves the primary connection elements. The metal lines are simplified to tap into these shared regions rather than creating complex routing networks, thereby reducing layout complexity while achieving compact integration.
Data Source
AI summary
The integrated circuit structure includes a substrate and a first resistive memory string over the substrate. The first resistive memory string includes memory cells, and each of the memory cells includes a word line transistor and a resistor. The word line transistor includes a channel region, a gate over the channel region, and a plurality of source/drain regions on opposite sides of the channel region. The resistor is over the word line transistor and is connected with the word line transistor in parallel. The word line transistors of two adjacent memory cells share a same one of the source/drain regions, and the memory cells are connected in series using the sharing ones of the source/drain regions.