Integrated Conductor Lines for High Power Semiconductor Impedance Matching
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Solution Overview
Problem
High power semiconductor devices face performance variability due to manufacturing tolerances in wire bond inductance, which is not sufficient for stringent requirements of new wireless communication systems, especially at high powers and frequencies, and existing integration methods increase cost and complexity while being limited to low power applications.
Innovation Solution
The solution involves forming high power semiconductor devices with integrated conductor lines on a semiconductor substrate, which serve as both connections to the active area and impedance matching components, using a thick dielectric layer and copper conductor lines to achieve high Q factors and reduce EM losses, thereby eliminating the need for wire bonds and simplifying manufacturing.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Reliability
If wire bonds are used to connect the active area to input and output leads, then the device can achieve impedance matching, but manufacturing tolerances cause variations in inductance that affect performance reliability
Solution Approach 1:
The patent merges the connection function and impedance matching function into a single integrated structure. The conductor lines are formed as part of the substrate packaging structure, combining the wire bond connection role with the impedance matching network role, eliminating the need for separate wire bonds and reducing the number of components that require precise manufacturing control
Solution Approach 2:
The conductor lines serve multiple functions simultaneously: they provide electrical connections between the active area and external leads, act as inductors in the impedance matching networks, and provide mechanical support. This multi-functionality reduces the overall complexity and number of components requiring precise manufacturing tolerances
2Reliability
If more wire bonds are used to achieve proper impedance matching, then the impedance matching performance improves, but the device complexity and manufacturing cost increase
Solution Approach 1:
The patent combines multiple functions into the conductor lines: electrical connection, inductance for impedance matching, and mechanical support. This integration reduces the total number of discrete components (wire bonds and separate impedance matching elements) while maintaining or improving impedance matching performance
Solution Approach 2:
The conductor lines are designed to perform multiple functions simultaneously, reducing the overall component count. The same conductor lines that provide electrical connections also serve as the inductors in the impedance matching networks, eliminating the need for additional wire bonds and separate matching components
3Manufacturing precision
If wire bond configuration is tightly controlled during manufacturing, then inductance variations are reduced, but manufacturing complexity and cost increase
Solution Approach 1:
The patent integrates the impedance matching function into the substrate packaging structure itself, forming conductor lines directly on the substrate. This eliminates the need for separate wire bonding processes and the associated tight tolerance requirements, as the conductor lines are formed using standard PCB fabrication techniques with inherent precision
Solution Approach 2:
The patent replaces the mechanical wire bonding process with a printed circuit board fabrication process. Instead of using wire bonding tools that require tight tolerance control, the conductor lines are formed using photolithography and etching processes that provide consistent, repeatable dimensions with standard manufacturing tolerances
Applied Scientific Principles
This section explains which scientific principles are used to turn an abstract innovation direction into a practical engineering solution.
Function Achieved in This Case
This approach ensures reliable high power semiconductor device performance by controlling conductor line parameters, achieving Q factors greater than 40 at powers exceeding 5 Watts and frequencies up to several GHz, while reducing manufacturing complexity and cost.
Implementation Method 1
using a thick dielectric layer and copper conductor lines to achieve high Q factors and reduce EM losses
Data Source
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Figure 3~4
AI summary
A high power semiconductor device (400) for operation at powers greater than 5 watts for wireless applications comprises a semiconductor substrate (402) including an active area (404) of the high power semiconductor device, contact regions (408) formed on the semiconductor substrate providing contacts to the active area of the high power semiconductor device, a dielectric layer (412) formed over a part of the semiconductor substrate, a lead (500, 502) for providing an external connection to the high power semiconductor device (400) and an impedance matching network (510, 512) formed on the semiconductor substrate (402) between the active area (404) of the high power semiconductor device and the lead (500, 502). The impedance matching network includes conductor lines (414) formed on the dielectric layer. The conductor lines (414) are coupled to the contact regions for providing high power connections to the contact regions of the active area, and have a predetermined inductance for impedance matching.