Integrated Deglitcher Circuit With Non-Overlap Timing
Find Innovative SolutionsGenerate Solutions
Solution Overview
Problem
Conventional output drivers experience significant signal propagation delay due to both deglitcher and nonoverlap blocks, which are essential for suppressing glitches and ensuring transistors are not on simultaneously, but reducing this delay without affecting performance is challenging as it can allow unwanted glitches to pass through.
Innovation Solution
The integration of nonoverlap delay into the deglitcher delay, utilizing two deglitcher circuits with distinct delays (tDLY1 and tNOL) that work in tandem to maintain performance while reducing total driver delay, by using RC circuits to control edge delays and mode control signals for glitch suppression and nonoverlap functionality.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Reliability
If the deglitcher delay is increased to suppress glitches, then glitch suppression performance is improved, but the total driver delay increases
Solution Approach 1:
The patent combines the deglitcher delay and nonoverlap delay into a single integrated delay mechanism. The nonoverlap delay is embedded within the deglitcher delay path, allowing both functions to share the same delay resources. This merging eliminates the need for separate delay blocks and reduces the total delay while maintaining both glitch suppression and nonoverlap functionality.
Solution Approach 2:
The delay block is designed to serve multiple functions simultaneously: it acts as both the deglitcher delay (filtering short glitches) and the nonoverlap delay (ensuring transistors are not on simultaneously). By making the delay mechanism universal, the patent avoids duplicating delay functionality and reduces the overall driver delay while maintaining both performance requirements.
2Reliability
If the nonoverlap delay is increased to ensure transistors are not on simultaneously, then transistor safety is improved, but the total driver delay increases
Solution Approach 1:
The nonoverlap delay is merged into the deglitcher delay path, where it shares the same delay resources. The nonoverlap function is implemented as part of the deglitcher circuitry, allowing both the nonoverlap safety function and glitch suppression to operate within a unified delay structure, thereby reducing total delay.
Solution Approach 2:
The delay mechanism is designed to be universal, serving both as the nonoverlap delay for transistor safety and as the deglitcher delay for glitch suppression. This multi-functionality eliminates redundant delay blocks and reduces the overall driver delay while maintaining both safety and performance requirements.
3Speed
If the driver delay is reduced to increase speed, then signal propagation speed is improved, but glitch suppression performance deteriorates
Solution Approach 1:
By merging the nonoverlap delay into the deglitcher delay, the patent creates a unified delay structure that provides both functions within a single delay path. This integration allows the system to achieve faster signal propagation by eliminating redundant delay stages while maintaining adequate glitch suppression through the combined delay function.
Solution Approach 2:
The integrated delay block serves multiple functions simultaneously, providing both glitch suppression and nonoverlap timing control. This universality allows the system to reduce overall delay and increase signal propagation speed while maintaining the necessary glitch filtering capability through the multi-functional delay mechanism.
Data Source
AI summary
A driver circuit includes a first deglitcher circuit that delays a rising edge or a falling edge of an input signal according to a mode control signal and supplies a first output signal. A second deglitcher circuit receives the first output signal and delays either a rising edge or a falling edge of the first output signal by a second delay according to the mode control signal and supplies a second output signal. Logic gates combine the first and second output signals to supply gate control signals for output transistors to drive the driver circuit output. A sum of the first delay and the second delay determines the total deglitch time defining a pulse width of pulses that are suppressed by the driver circuit and the second delay determines a non-overlap time. The non-overlap time overlaps in time with the total deglitch time.