Integrated Inductor Structure for High-Frequency Q Factor
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Solution Overview
Problem
Conventional integrated inductors face challenges in achieving high quality factor Q, large bandwidth, and symmetry due to parasitic capacitances, metal loss, and asymmetry, which affect their performance in differential circuits and high-frequency operations.
Innovation Solution
The integrated inductor structure features an outer and inner metal segment on different layers, with bridging and connecting structures to reduce parasitic capacitances and enhance symmetry, allowing for improved quality factor Q and bandwidth by optimizing metal layer placement and resistance.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Quantity of substance
If the number of turns of the metal segment is increased to enhance inductance, then the inductance increases, but the parasitic series resistance and parasitic capacitance increase, which decrease the quality factor Q and self-resonant frequency
Solution Approach 1:
The patent transitions from a planar spiral structure to a three-dimensional stacked structure with metal segments on different layers connected by via holes. This dimensional change allows the inductor to achieve higher inductance through vertical stacking rather than increasing the number of turns in a single plane, thereby reducing parasitic effects while maintaining or enhancing inductance.
Solution Approach 2:
The inductor is divided into multiple metal segments located on different layers, connected through via holes. This segmentation allows the current path to be distributed across multiple segments and layers, reducing the parasitic series resistance and capacitance that would accumulate in a single continuous spiral trace.
2Quantity of substance
If the area of the inductor is increased to enhance inductance, then the inductance increases, but the displacement current and eddy current losses increase, which decrease the quality factor Q
Solution Approach 1:
By stacking metal segments vertically on different layers, the patent achieves higher inductance without proportionally increasing the planar area. The vertical dimension provides additional inductance through the stacked configuration, reducing the need to expand the footprint area and thereby minimizing substrate losses.
Solution Approach 2:
Dielectric layers are introduced between the metal segments on different layers. These dielectric intermediaries reduce the coupling between adjacent metal segments, minimizing displacement currents and eddy currents in the substrate, thereby reducing substrate losses while maintaining the stacked inductor configuration.
3Stability of the object's composition
If a symmetric spiral inductor structure is used to improve symmetry, then the symmetry improves, but the current path resistance increases due to multiple connecting structures and bridging segments
Solution Approach 1:
The patent uses vertical stacking on different layers to achieve symmetry rather than relying on planar symmetric patterns. This allows the inductor to maintain good symmetry for differential circuits while using fewer connecting structures, as the vertical arrangement naturally provides balanced current paths without requiring multiple bridging segments.
4Ease of manufacture
If a planar spiral structure is used to simplify manufacturing, then the manufacturing is simpler, but the parasitic capacitance between adjacent metal segments increases
Solution Approach 1:
The patent transitions from planar to three-dimensional stacked structure, which reduces parasitic capacitance by separating metal segments vertically with dielectric layers. While this adds manufacturing steps for multi-layer deposition and via formation, it significantly reduces the parasitic effects that plague planar spirals, making it suitable for high-frequency applications.
Data Source
AI summary
This invention discloses a structure of an integrated inductor, comprising: an outer metal segment which comprises a first metal sub-segment and a second metal sub-segment; an inner metal segment which is arranged inside an area surrounded by the outer metal segment and comprises a third metal sub-segment and a fourth metal sub-segment; and at least a connecting structure for connecting the outer metal segment and the inner metal segment. The first metal sub-segment corresponds to the third metal sub-segment, and the first metal sub-segment and the third metal sub-segment belong to different metal layers in a semiconductor structure. The second metal sub-segment corresponds to the fourth metal sub-segment, and the second metal sub-segment and the fourth metal sub-segment belong to different metal layers in a semiconductor structure.