Integrated LC Mounting Structure for Low-Parasitic Current Paths
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Solution Overview
Problem
Existing technologies face challenges in reducing parasitic resistance and parasitic inductance in current paths, particularly in integrated circuit configurations involving inductors and capacitors.
Innovation Solution
An integrated LC device comprising a capacitor layer, a rewiring layer, and an inductor layer, where the inductor is electrically connected to the capacitor via via conductor portions and wiring, reducing the length of the current path and minimizing parasitic effects.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Power
If a combination of inductor and capacitor is used in a power supply line, then power conversion function is achieved, but parasitic resistance and parasitic inductance increase
Solution Approach 1:
The patent combines the inductor and capacitor into a single integrated LC device structure where both components are formed within the same device layer. This integration reduces the physical separation between components and minimizes the length of current paths, thereby reducing parasitic resistance and inductance while maintaining the power conversion function.
Solution Approach 2:
The patent utilizes vertical stacking in the thickness direction to arrange the capacitor layer and inductor layer at different heights. This three-dimensional arrangement reduces the planar footprint and shortens current paths compared to traditional planar layouts, effectively reducing parasitic effects while maintaining electrical functionality.
2Device complexity
If inductor and capacitor are integrated on circuit board, then device complexity is reduced, but current path length increases
Solution Approach 1:
The patent employs vertical stacking where the capacitor layer and inductor layer are positioned at different heights in the thickness direction. This three-dimensional configuration allows direct vertical connections between components, dramatically shortening current paths compared to planar arrangements while achieving integration.
Solution Approach 2:
The patent introduces via conductor portions as intermediary elements that provide direct vertical electrical connections between the capacitor layer and inductor layer. These via conductors act as mediators that eliminate the need for long lateral routing paths, thereby reducing parasitic effects while maintaining integration.
Data Source
AI summary
An integrated LC device includes: a capacitor layer which has a first surface and a second surface, the first surface and the second surface facing each other in a thickness direction; a rewiring layer which is provided on the first surface of the capacitor layer; and an inductor layer which is provided on the second surface of the capacitor layer. The capacitor layer includes a capacitor portion having an anode and a cathode, a first insulating portion provided around the capacitor portion, and a first via conductor portion penetrating through the first insulating portion in the thickness direction at a position separate from the capacitor portion in a plane direction orthogonal to the thickness direction. The rewiring layer includes a wiring portion and a second insulating portion provided around the wiring portion. The inductor layer 30 includes an inductor portion and a third insulating portion provided around the inductor portion.