Integrated Circuit Scan Testing for Unused Memory Address Latches
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Solution Overview
Problem
In compiled memories, unused address latches due to unneeded pins result in reduced fault coverage during scan testing, as their inputs are permanently tied to power supply nodes, making them untestable and reducing the effectiveness of automatic test pattern generation.
Innovation Solution
Unused latches in compiled memories are connected to existing address pins, allowing them to change states during scan testing, thereby improving fault coverage by incorporating these latches into the scan chains.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Device complexity
If unused address latches are permanently tied to power supply nodes, then the compiled memory design is simplified, but fault coverage during scan testing is reduced
Solution Approach 1:
The patent applies dynamics by making the latch input connection changeable from a fixed power supply node to a configurable connection with existing address pins. This allows the latch to transition from an untestable static state to a testable dynamic state, enabling scan testing to exercise the latch while maintaining the simplified compiled memory design structure.
Solution Approach 2:
The patent changes the parameter of the latch input connection from a constant power supply node to a configurable connection that can be linked to existing address pins. This parameter change enables the latch to capture different values during scan testing, improving fault coverage without requiring a complete redesign of the memory architecture.
2Ease of manufacture
If unused address latches are permanently tied to power supply nodes, then the layout design is simplified, but scan testing effectiveness is reduced
Solution Approach 1:
The patent makes the latch input connection dynamic by allowing it to be configured to connect to existing address pins rather than being permanently tied to power supply nodes. This enables scan testing to effectively exercise the latch while maintaining the layout design simplifications of compiled memories.
Solution Approach 2:
The patent introduces existing address pins as an intermediary element that connects to the latch input. This intermediary allows the latch to be integrated into the scan testing process without requiring new external pins or complex layout changes, thus maintaining ease of manufacture while improving testing effectiveness.
3Quantity of substance
If compiled memories use fewer external control pins, then the memory size is reduced, but fault coverage for unused logic is reduced
Solution Approach 1:
The patent applies universality by making existing address pins serve multiple functions: they continue to provide address input for used latches while also serving as input sources for unused latches during scan testing. This multi-functionality allows the same pins to support both normal operation and testing, improving fault coverage without increasing the number of external control pins.
Solution Approach 2:
The patent changes the functional parameter of existing address pins from solely address input to also serving as test input for unused latches. This parameter change enables comprehensive fault coverage for unused logic while maintaining the reduced pin count that characterizes compiled memories with smaller memory sizes.
Data Source
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AI summary
A system includes test control circuitry and a memory. The memory includes a memory array, a pre-decode circuit, and a plurality of address latches. Each address latch of the plurality of address latches is configured to operate in a scan chain of a plurality of scan chains for scan testing. A first set of the plurality of address latches each has a data input coupled to a corresponding address pin of the first memory and each has an output coupled to the pre-decode circuit. A second set of the plurality of address latches, mutually exclusive of the first set, each has a data input coupled to a data input of at least one latch in the first set of the plurality of latches and each is configured to not provide any input to the pre-decode circuit.