Wafer-Level Integrated Plasma Power Limiter for Signal Integrity

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Solution Overview

Problem

Existing plasma power limiters are separate, bulky devices that cause significant signal loss and cannot be easily integrated into sensitive electronic circuits due to their design, making them unsuitable for applications where space and signal integrity are critical.

Innovation Solution

A monolithically fabricated wafer-level plasma power limiter is integrated onto the same substrate as other circuits using wafer-level processing, featuring a hermetically sealed cavity with ionizable gas and vertically extended probe tips that act as plasma triggers, allowing for controlled ionization and current sinking without signal loss.

Engineering Contradictions & Design Principles

VSEngineering Contradiction Analysis

1Reliability

If traditional separate plasma power limiters are used, then high-power signal protection is achieved, but device size increases and signal loss occurs

Engineering Contradiction:
Improveprotection from high-power signalsVSAvoiddevice size
Core Design Contradiction:
ReliabilityVSVolume of moving object

Solution Approach 1:

The plasma power limiter is merged with the semiconductor device by integrating the cavity structure directly into the device substrate. The cavity is formed within the semiconductor material itself, eliminating the need for separate external limiter devices while maintaining protection functionality.

Inventive Principle:
Principle #5Merging (Combining)

Solution Approach 2:

The cavity structure is nested within the semiconductor device substrate, with the cavity containing ionizable gas and being surrounded by conductive layers that are part of the semiconductor device structure. This nested arrangement allows the limiter function to be embedded within the device volume.

Inventive Principle:
Principle #7Nested doll (Nesting)

2Reliability

If traditional separate plasma power limiters are used, then high-power signal protection is achieved, but signal loss increases

Engineering Contradiction:
Improveprotection from high-power signalsVSAvoidsignal loss
Core Design Contradiction:
ReliabilityVSLoss of energy

Solution Approach 1:

By merging the plasma power limiter with the semiconductor device, the signal path is shortened and direct coupling is achieved between the device and the protective cavity structure, minimizing signal loss while maintaining protection capability.

Inventive Principle:
Principle #5Merging (Combining)

3Volume of moving object

If wafer-level integration is used, then device size is reduced, but manufacturing complexity increases

Engineering Contradiction:
Improvedevice sizeVSAvoidmanufacturing process
Core Design Contradiction:
Volume of moving objectVSEase of manufacture

Solution Approach 1:

The cavity structure, conductive layers, and ionizable gas are prepared and integrated into the semiconductor device during the wafer fabrication process itself, before final device assembly. This preliminary integration simplifies subsequent manufacturing steps despite the added initial complexity.

Inventive Principle:
Principle #10Preliminary action

Solution Approach 2:

Ionizable gas is introduced into the sealed cavity structures during wafer-level processing, utilizing gas handling techniques to fill and seal the cavities in an automated manner, which manages the manufacturing complexity of integrating gas-filled structures.

Inventive Principle:
Principle #29Pneumatics and hydraulics

Applied Scientific Principles

This section explains which scientific principles are used to turn an abstract innovation direction into a practical engineering solution.

Function Achieved in This Case

The integrated plasma power limiter effectively protects sensitive electronics from high-intensity signals by allowing low-intensity signals to pass through while ionizing and diverting high-intensity signals to ground, minimizing signal loss and enhancing the reliability of high-frequency receivers.

Implementation Method 1

A monolithically fabricated wafer-level plasma power limiter is integrated onto the same substrate as other circuits using wafer-level processing, featuring a hermetically sealed cavity with ionizable gas

Methodology Applied
Scientific EffectIonization: Ionisation

Implementation Method 2

when ionized becomes a plasma and allows electrical current to propagate therethrough

Methodology Applied
Scientific EffectPlasma: Plasma

Data Source

PatentEP2856643B1Integrated micro-plasma limiter
Publication Date: 2016.10.12 NORTHROP GRUMMAN SYSTEMS CORP
  • EP2856643B1 patent drawingFigure 1~2
  • EP2856643B1 patent drawingFigure 3~4

AI summary

A plasma power limiter fabricated using wafer-level fabrication techniques with other circuit elements. The plasma limiter includes a signal substrate and a trigger substrate defining a hermetically sealed cavity therebetween in which is encapsulated an ionizable gas. The signal substrate includes a signal line within the cavity and the trigger substrate includes at least one trigger probe extending from the trigger substrate towards the transmission line. If a signal propagating on the transmission line exceeds a power threshold, the gas within the cavity is ionized creating a conduction path between the transmission line and the trigger probe that draws off the high power current.