Integrated Power Stage and Control Die Package Design
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Solution Overview
Problem
Intelligent power modules face limitations in speed and efficiency due to the impedance of the control signal loop, which is exacerbated by the separation of components and reliance on a common underlying circuit like a PCB, leading to voltage overshoot that interferes with signal transmission.
Innovation Solution
A semiconductor package design that integrates a power stage and control die on opposing surfaces of leadframes, providing a ground return path within the package, which reduces signal impedance and facilitates conductive cooling, thereby mitigating voltage overshoot and enabling higher frequency communications.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Ease of manufacture
If components are separated and interconnected through a common underlying circuit like PCB, then ease of manufacture and assembly is improved, but signal impedance increases leading to voltage overshoot and reduced communication speed
Solution Approach 1:
The patent merges the control die and power stage into a single integrated package, eliminating the need for external PCB interconnections. This integration reduces the signal loop area and impedance, enabling faster communication between control and power components while maintaining manufacturing efficiency through standardized packaging processes.
Solution Approach 2:
The patent transitions from a planar PCB layout to a three-dimensional stacked architecture where the control die and power stage are vertically arranged within the same package. This dimensional change dramatically reduces the signal path length and loop area, thereby reducing impedance and enabling higher frequency communications.
2Speed
If control die and power stage are integrated within a single package, then signal impedance is reduced and communication speed is improved, but device complexity and manufacturing difficulty increase
Solution Approach 1:
The patent segments the integrated package into distinct functional layers: a control die layer, a power stage layer, and an intermediate substrate layer. This segmentation allows each component to be manufactured and tested separately before assembly, reducing overall device complexity while maintaining the benefits of integration for high-speed communication.
Solution Approach 2:
The patent introduces an intermediate substrate or carrier board within the package that serves as a mediator between the control die and power stage. This intermediary provides standardized connection interfaces, simplifies thermal management, and reduces packaging complexity by providing a modular assembly approach.
3Reliability
If ground return path is provided within the package, then signal impedance is reduced and voltage overshoot is mitigated, but manufacturing precision requirements increase
Solution Approach 1:
The patent merges the ground return path with the power and signal traces within the integrated package, creating a tightly coupled current loop. This merging minimizes the loop area and reduces inductance, improving signal integrity and reducing voltage overshoot while using standard manufacturing tolerances through co-planar or adjacent trace routing.
Applied Scientific Principles
This section explains which scientific principles are used to turn an abstract innovation direction into a practical engineering solution.
Function Achieved in This Case
This design reduces signal loop impedance, allowing for higher frequency communications and improved heat dissipation, enhancing the reliability and efficiency of power switching operations, particularly in high-voltage applications.
Implementation Method 1
a second leadframe that provides a ground return path within the package and facilitates conductive cooling from the semiconductor die
Implementation Method 2
Including a ground return path within the package provides for a lower impedance for electronic signals between the semiconductor die and a control die
Data Source
AI summary
A package includes a semiconductor die forming a power field effect transistor (FET), a control die, and a first leadframe. The control die is arranged on a first surface of the first leadframe, and the semiconductor die is arranged on an opposing second surface of the first leadframe. The package further includes a second leadframe including a first surface and a second surface opposing the first surface, wherein the semiconductor die is arranged on the first surface of the second leadframe to facilitate heat transfer therethrough. The package also includes mold compound at least partially covering the semiconductor die, the control die, the first leadframe and the second leadframe with the second surface of the second leadframe exposed.