Integrated Selection Gate Structure for Non-Volatile Memory
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Solution Overview
Problem
The challenge in non-volatile semiconductor memory devices is the increase in chip area due to the number of laminated layers, which results in higher word line drivers and wirings, and the inefficiency of write operations caused by integrally configuring drain and source selection gates.
Innovation Solution
Configuring the drain and source selection gates on the same level and forming them integrally, with a higher impurity concentration in the source side selection gate to ensure proper write operations, and optionally interposing global selection gates to control voltage transfer.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Quantity of substance
If the number of laminated layers is increased to increase storage capacity, then the storage capacity is improved, but the chip area increases due to more word line drivers and wirings
Solution Approach 1:
The patent merges the drain selection gate and source selection gate into a single integrated selection gate structure. This consolidation reduces the total number of selection gates from four (two per pillar) to two (one shared structure), thereby reducing the number of wirings and drivers needed, which suppresses chip area enlargement while maintaining the ability to perform write operations on multi-laminated memory layers
Solution Approach 2:
The integrated selection gate structure serves multiple functions simultaneously: it acts as both the drain selection gate and source selection gate for different pillars, and enables selective write operations to multiple memory layers. This multi-functional design reduces the overall wiring complexity and driver count while maintaining storage capacity expansion capabilities
2Device complexity
If the drain and source selection gates are integrally configured, then the device complexity is reduced, but the write operation efficiency deteriorates due to insufficient voltage transfer to the source side
Solution Approach 1:
The patent applies local quality by creating an impurity concentration gradient within the integrated selection gate structure. The source side of the selection gate is doped with higher impurity concentration than the drain side, which locally enhances electrical conductivity and reduces resistance on the source side. This localized modification ensures adequate voltage transfer to the source side while maintaining the integral configuration, thereby resolving the write operation efficiency issue
Solution Approach 2:
The patent changes the electrical parameter (impurity concentration) of the selection gate material to optimize performance. By increasing the impurity concentration on the source side of the integrated selection gate, the electrical conductivity is improved, reducing resistance and enabling sufficient voltage transfer for effective write operations, thus maintaining both integral configuration and write efficiency
Applied Scientific Principles
This section explains which scientific principles are used to turn an abstract innovation direction into a practical engineering solution.
Function Achieved in This Case
This configuration reduces the number of selection gates and wirings, minimizing chip area and improving operational speed by ensuring adequate write operations and reducing resistance in the selection gates.
Implementation Method 1
a higher impurity concentration in the source side selection gate to ensure proper write operations
Implementation Method 2
reducing resistance in the selection gates
Data Source
AI summary
According to one embodiment, a non-volatile semiconductor memory device comprises memory strings. Each memory string comprises a semiconductor layer, control gates, a first selection gate, and a second selection gate. A semiconductor layer comprises a pair of pillar portions which extend in a vertical direction to a substrate, and a coupling portion formed to couple the pair of pillar portions. Control gates orthogonally intersect one of the pair of pillar portions or the other of the pair of pillar portions. A first selection gate orthogonally intersects one of the pair of pillar portions and is formed above the control gates. A second selection gate orthogonally intersects the other of the pair of pillar portions, is formed above the control gates, and is on the same level as the first selection gate as well as integrated with the first selection gate.