Integrated Timing Models for Digital Circuit Design
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Solution Overview
Problem
Current auto-place-route (APR) tools cannot read and analyze all extracted timing models (ETMs) for a single digital circuit design across different operating modes, leading to incomplete timing information analysis.
Innovation Solution
Integrate multiple extracted timing models into two special ETMs (NOCV ETM and OCV ETM) to reduce the number of models read by the APR tool, where the NOCV ETM excludes on-chip variation factors, allowing for comprehensive static timing analysis.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Reliability
If multiple extracted timing models (ETMs) are generated for different operating modes, then timing analysis completeness is improved, but device complexity and processing difficulty increase
Solution Approach 1:
The patent combines multiple ETM files corresponding to different operating modes into a single integrated ETM file. The integration process merges timing arcs, logic gate delays, and setup/hold margin factors from individual ETMs into unified structures, allowing the APR tool to read one comprehensive file instead of multiple separate files, thus resolving the contradiction between completeness and complexity
Solution Approach 2:
The integrated ETM file serves as a universal timing model that contains timing information for all operating modes within a single file. This multi-functional structure allows the APR tool to perform timing analysis across different operating modes without needing to switch between multiple specialized ETM files, reducing processing complexity while maintaining comprehensive coverage
2Measurement precision
If the APR tool reads all ETMs for different operating modes, then timing information accuracy is improved, but processing time and computational resources increase
Solution Approach 1:
The patent performs preliminary integration of multiple ETM files into a single comprehensive ETM file before the APR tool executes timing analysis. This pre-processing step consolidates all timing information in advance, so the APR tool can directly read and process one unified file without needing to individually read, parse, and merge multiple separate ETM files during the main analysis phase, thereby reducing computational overhead and processing time
3Manufacturing precision
If on-chip variation (OCV) factors are included in all ETMs, then manufacturing variation accuracy is improved, but analysis complexity and derating requirements increase
Solution Approach 1:
The patent applies different OCV treatment strategies to different parts of the integrated ETM structure. The integration process selectively handles OCV factors based on their applicability to specific operating modes, allowing some regions of the timing model to include detailed variation information while other regions use simplified models, thus reducing overall analysis complexity while maintaining manufacturing precision where critical
Data Source
AI summary
A timing analysis method for a digital circuit design, a system and a computer readable storage media thereof are provided. The timing analysis method includes following steps. An integrated circuit (IC) design is obtained, wherein the IC is operated in a plurality of operating modes. A plurality of extracted timing models (ETMs) are respectively generated according to the operating modes of the IC design, wherein each of the ETMs includes a none on-chip variation (NOCV) part and an on-chip variation (OCV) part. The ETMs corresponding to the operating modes are integrated into a NOCV ETM and an OCV ETM, wherein the OCV part of the operating modes is not considered when the NOCV ETM is generated. And, a timing checking of the IC design is analyzed according to the NOCV ETM and the OCV ETM.