Inter-Core Communication Unit for Multi-Core Processor Latency
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Solution Overview
Problem
In multi-core processor integrated circuits, efficient communication between processor units is hindered by unpredictable memory access delays and high latency, which is critical for real-time data processing in applications like software defined radio and LTE systems.
Innovation Solution
A shared inter-core communication unit manages token memories, enabling efficient data transfer between processor cores through commands like get_data() and send_data(), ensuring predictable memory access and low latency by connecting token memories directly with processor cores.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Loss of time
If traditional memory access methods are used in multi-core processors, then device complexity is reduced, but memory access latency increases and becomes unpredictable
Solution Approach 1:
The patent introduces an intermediary communication mechanism between processor cores that uses token-based signaling and dedicated communication paths. This mediator approach allows predictable handshaking and data transfer protocols that reduce latency while managing the added architectural complexity through standardized interfaces.
Solution Approach 2:
The communication architecture is segmented into distinct functional components: producer cores, consumer cores, token memory buffers, and control logic. This segmentation allows each component to operate independently with well-defined interfaces, making the system more manageable despite the increased complexity, and enabling optimized data flow paths that reduce latency.
2Productivity
If data transfer between processor cores is optimized for speed, then productivity increases, but energy consumption increases
Solution Approach 1:
The communication mechanism uses periodic token-based signaling to initiate data transfers only when needed, rather than maintaining continuous high-speed transfer paths. This periodic activation of communication resources allows high throughput during active transfer windows while minimizing energy consumption during idle periods between transfers.
Solution Approach 2:
The patent implements continuous data processing pipelines where producer and consumer cores operate continuously, but the actual high-speed data transfer occurs only when tokens are exchanged. This maintains productivity through continuous computation while reducing energy consumption by limiting high-speed communication to necessary transfer moments rather than continuous operation.
3Reliability
If memory access is made predictable for real-time processing, then reliability improves, but device complexity increases
Solution Approach 1:
The communication architecture incorporates feedback mechanisms where consumer cores send acknowledgment tokens to producer cores, and the system state is continuously monitored and adjusted. This feedback loop ensures predictable data availability and access patterns, improving reliability for real-time processing while managing complexity through systematic control protocols.
Solution Approach 2:
The system performs preliminary actions by pre-establishing communication protocols, token allocation schemes, and data flow patterns before actual data transfer occurs. This preparation creates predictable access patterns for real-time processing while containing complexity through standardized preliminary configuration rather than complex runtime decision-making.
Data Source
AI summary
Method, apparatus, and computer program product embodiments of the invention are disclosed for efficient communication between processor units in a multi-core processor integrated circuit architecture. In example embodiments of the invention, a method comprises: storing with a shared inter-core communication unit in a multi-core processor, first data produced by a producer processor core, in a first token memory located at a first memory address of a memory address space; and connecting with the shared inter-core communication unit, the first token memory to a consumer processor core of the multi-core processor, to load the first data from the first token memory into the consumer processor core, in response to a first-type command from the producer processor core.