Inter-Metal Dielectric Reliability Checks with Parasitic Voltage Analysis
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Solution Overview
Problem
The reliability of semiconductor devices is compromised by dielectric breakdowns due to high voltage differences between metal components, exacerbated by shrinking device sizes, and existing reliability tests are time-consuming.
Innovation Solution
A method using electronic design automation (EDA) tools to perform efficient dielectric breakdown reliability checks by calculating internal voltage differences based on parasitic effects, tagging components exceeding a voltage threshold, and optimizing design rules to prevent dielectric breakdown.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Reliability
If existing reliability tests are performed to check dielectric breakdown, then reliability can be assessed, but the testing process is time-consuming
Solution Approach 1:
The patent performs reliability checks during the design phase using EDA tools to calculate voltage differences and identify potential dielectric breakdown risks before manufacturing. This preliminary action allows the system to assess reliability early in the development process, eliminating the need for time-consuming physical testing after fabrication.
Solution Approach 2:
The patent replaces physical reliability testing with computational methods using EDA tools. Instead of performing actual electrical stress tests on fabricated devices, the system uses computer-based voltage difference calculations and design rule checks to predict and prevent dielectric breakdown, significantly reducing testing time.
2Productivity
If device sizes are shrunk to increase circuit density, then more functionality is achieved, but voltage differences between metal components increase causing dielectric breakdown
Solution Approach 1:
The patent implements a feedback mechanism where EDA tools continuously calculate voltage differences between metal components during the design process. When voltage differences approach thresholds that could cause dielectric breakdown, the system provides feedback to designers to adjust spacing or routing, allowing high-density designs to maintain reliability.
Solution Approach 2:
The patent changes design parameters such as metal component spacing and routing paths to control voltage differences. By adjusting these parameters during the design phase, the system enables tighter spacing for higher circuit density while maintaining voltage levels below breakdown thresholds through computational optimization.
3Productivity
If metal components are spaced closer to increase circuit density, then productivity improves, but voltage differences increase exceeding dielectric breakdown thresholds
Solution Approach 1:
The patent introduces EDA tools as an intermediary between design requirements and physical implementation. These tools calculate voltage differences and provide design rule recommendations that mediate between the desire for close spacing (high density) and the need to maintain voltage below breakdown thresholds, enabling safe high-density designs.
Solution Approach 2:
The patent performs voltage difference calculations and design rule checks during the design phase before fabrication. This preliminary action identifies potential harmful voltage differences early, allowing designers to adjust layouts to prevent dielectric breakdown while maintaining high circuit density through optimized component spacing.
Data Source
AI summary
The present disclosure provides a method and a non-transitory computer readable media for inter-metal dielectric reliability check. The method comprises: receiving an electronic layout, the electronic layout including a first plurality of electrical components in a first layer; determining an internal voltage difference within each electrical component in the first layer based on parasitic effect; generating a simulation voltage value for each electrical component in the first layer based on the internal voltage differences; and tagging a pair of electrical components in the first layer when a first voltage difference between the pair of electrical components exceeds a first voltage threshold. The first voltage difference is determined based on the simulation voltage value of each electrical component.