Semiconductor Interconnect Air-Gap Structure to Prevent Metal Chamfering

Resolve Bottlenecks,
Find Innovative Solutions
Generate Solutions

Solution Overview

Problem

The increase in back-end metal interconnection RC delay in semiconductor structures, such as DRAMs, due to metal chamfering and collapse during etching, and the resulting risk of cracks in the metal layer, which hinders performance improvement.

Innovation Solution

A method involving the formation of a protective layer over a conductive layer, followed by etching to create a trench that penetrates through both layers, allowing for the filling of a dielectric layer with an air gap that extends into the protective layer, thereby reducing chamfering and collapse and increasing air gap height to minimize metal cracks.

Engineering Contradictions & Design Principles

VSEngineering Contradiction Analysis

1Reliability

If low dielectric constant materials are introduced to reduce RC delay, then interconnection performance is improved, but metal chamfering and collapse occur during etching

Engineering Contradiction:
Improveinterconnection performanceVSAvoidmetal profile integrity
Core Design Contradiction:
ReliabilityVSManufacturing precision

Solution Approach 1:

A protective layer is introduced as an intermediary between the metal interconnect and the etching process. This protective layer acts as a mediator that prevents direct interaction between the etchant and metal surfaces, thereby eliminating chamfering and collapse while allowing the low dielectric constant material to fulfill its performance function.

Inventive Principle:
Principle #24Intermediary (Mediator)

Solution Approach 2:

The protective layer is formed in advance before the etching process. This preliminary action prepares the structure to resist subsequent etching damage, preventing metal profile degradation before it can occur during the low dielectric constant material formation process.

Inventive Principle:
Principle #10Preliminary action

2Reliability

If air gaps are formed to reduce parasitic capacitance, then interconnection performance is improved, but the risk of metal cracks increases due to low air gap height

Engineering Contradiction:
Improveparasitic capacitance reductionVSAvoidmetal layer integrity
Core Design Contradiction:
ReliabilityVSStrength

Solution Approach 1:

The protective layer is formed in advance to enable the creation of taller air gaps. This preliminary structural preparation allows the air gap to extend higher without compromising metal integrity, as the protective layer supports the overall structure during and after air gap formation.

Inventive Principle:
Principle #10Preliminary action

Solution Approach 2:

The structure combines multiple materials including the protective layer, metal interconnect, low dielectric constant material, and air gap. This composite structure distributes mechanical stresses and electrical fields across different materials, reducing parasitic capacitance while maintaining metal layer strength through the synergistic combination of components.

Inventive Principle:
Principle #40Composite materials

Applied Scientific Principles

This section explains which scientific principles are used to turn an abstract innovation direction into a practical engineering solution.

Function Achieved in This Case

This approach effectively reduces metal chamfering and collapse, increases air gap height, and enhances the performance of semiconductor structures by minimizing the risk of metal cracks and improving interconnection reliability.

Implementation Method 1

depositing the dielectric material on the surface of the second adhesive layer by a plasma-enhanced chemical vapor deposition process

Methodology Applied
Scientific EffectPlasma-enhanced chemical vapor deposition: Plasma Enhanced Chemical Vapour Deposition

Data Source

PatentUS12051618B2Methods for forming semiconductor structures and semiconductor structures
Publication Date: 2024.07.30 CHANGXIN MEMORY TECH INC
  • US12051618B2 patent drawing
  • US12051618B2 patent drawing
  • US12051618B2 patent drawing

AI summary

The present invention relates to the technical field of semiconductor manufacturing, and in particular, to a method for forming a semiconductor structure and a semiconductor structure. The method for forming a semiconductor structure comprises: forming an interconnect layer and a conductive layer covered on a surface of the interconnect layer; forming a protective layer covering a surface of the conductive layer away from the interconnect layer; forming a trench penetrating the protective layer and the conductive layer; and filling a dielectric layer in the trench, and forming an air gap in the dielectric layer, the air gap extending from the trench in the conductive layer into the trench in the protective layer.