High Performance Interconnect Architecture for Server Bandwidth
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Solution Overview
Problem
Current interconnect architectures in computing systems face challenges in meeting the increasing demand for higher performance and power efficiency, particularly in servers and mobile devices, as they struggle to handle the complexity of advanced component communication and bandwidth requirements.
Innovation Solution
The development of a high-performance interconnect architecture that incorporates point-to-point links, retimer devices, and advanced signaling techniques such as pulse amplitude modulation (PAM), along with enhanced equalization circuits and error correction mechanisms, to support higher speeds and wider lane widths, ensuring efficient data transmission across multiple processors and devices.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Speed
If traditional multi-drop buses are used for interconnect, then device complexity is reduced, but communication bandwidth and speed are insufficient for modern processing demands
Solution Approach 1:
The interconnect architecture is segmented into multiple point-to-point links instead of using a single multi-drop bus. Each link operates independently at high speed, allowing parallel communication between processor sockets and other devices. This segmentation enables the system to achieve higher aggregate bandwidth while maintaining manageable complexity through modular design.
Solution Approach 2:
The architecture transitions from a single-dimensional multi-drop bus topology to a multi-dimensional mesh-like interconnect fabric. This dimensional change allows data to flow through multiple paths simultaneously, increasing communication speed and bandwidth while distributing the complexity across multiple routing dimensions rather than concentrating it in a single bus structure.
2Productivity
If higher data transmission speeds are implemented, then bandwidth increases, but signal integrity and error rates become problematic
Solution Approach 1:
The interconnect architecture incorporates feedback mechanisms including acknowledgment packets, error detection and correction codes, and automatic retry logic. When signals are transmitted at high speeds, the feedback system monitors for errors and requests retransmission when necessary, ensuring data integrity is maintained despite the increased transmission rate and potential signal degradation.
Solution Approach 2:
Error correction codes and validation checks are embedded in the data transmission protocol before signals are sent at high speeds. This beforehand cushioning prepares the system to handle potential signal integrity issues by pre-establishing error detection and correction capabilities, allowing the system to maintain reliability even when operating at maximum transmission rates.
3Productivity
If more processing power is integrated into single devices, then device count decreases, but interconnect bandwidth demand increases
Solution Approach 1:
The interconnect bandwidth demand is segmented across multiple point-to-point links rather than requiring a single high-capacity bus. Each link handles a portion of the total bandwidth requirement, allowing the system to support multiple high-performance processor sockets simultaneously. This segmentation of bandwidth demand enables scaling of processing power without proportionally increasing the complexity of any single interconnect channel.
Applied Scientific Principles
This section explains which scientific principles are used to turn an abstract innovation direction into a practical engineering solution.
Function Achieved in This Case
This solution enables higher bandwidth and lower latency communication, supporting speeds up to 32 GT/s and wider lane widths, while maintaining power efficiency and backward compatibility, thus addressing the complexity and performance demands of modern computing systems.
Implementation Method 1
advanced signaling techniques such as pulse amplitude modulation (PAM)
Implementation Method 2
enhanced equalization circuits
Data Source
AI summary
A device includes a receiver to receive one or more training sequences during a training of a link, where the link connects two devices. The device may include agent logic to determine, from the one or more training sequences, a number of extension devices on the link between the two devices, and determine that the number of extension devices exceeds a threshold number. The device may include a transmitter to send a plurality of clock compensation ordered sets on the link based on determining that the number of extension devices exceeds a threshold number.