Interconnect Structure With Selective Barrier Layers for Lower RC Delay
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Solution Overview
Problem
The increasing density and reduced dimensions of semiconductor elements in integrated circuits lead to higher electrical resistivity and resistive-capacitive (RC) delay in back-end-of-line interconnect structures, necessitating improved methods for forming interconnect structures.
Innovation Solution
The formation of interconnect structures involves the use of a selective deposition process for barrier layers and conductive materials, including a blocking layer to prevent metal diffusion, followed by an anneal process to enhance miscibility and stability, resulting in conductive lines with reduced resistance and improved thermal stability.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Productivity
If the density of semiconductor elements is increased and dimensions are reduced, then more functionality and higher performance are achieved, but electrical resistivity and RC delay increase
Solution Approach 1:
The patent applies different materials with different properties to different regions of the interconnect structure. Specifically, it uses a first conductive material (e.g., tungsten) for via regions and a second conductive material (e.g., copper or cobalt) for line regions, optimizing each region's electrical properties for its specific function while maintaining overall high density and low RC delay
Solution Approach 2:
The patent employs composite interconnect structures combining multiple conductive materials and dielectric materials with different properties. The interconnect structure integrates conductive vias, conductive lines, and dielectric layers with varying permittivity values to achieve both high device density and reduced electrical resistance, resolving the contradiction between productivity and reliability
2Ease of manufacture
If conventional deposition processes are used for barrier layers, then manufacturing is simpler, but metal diffusion occurs and thermal stability is reduced
Solution Approach 1:
The patent introduces a blocking layer as an intermediary between the dielectric layer and the barrier layer. This blocking layer prevents metal diffusion into the dielectric material and improves thermal stability during subsequent processing steps, while the barrier layer selectively prevents diffusion at the conductive material interface. This multi-layer approach maintains manufacturing feasibility while significantly improving compositional stability
Solution Approach 2:
The patent segments the diffusion barrier function into multiple distinct layers: a blocking layer for preventing metal diffusion into the dielectric and a barrier layer for preventing diffusion at the conductive interface. This segmentation allows each layer to be optimized for its specific function, with the blocking layer providing thermal stability and the barrier layer providing diffusion prevention, thereby improving overall composition stability without excessive manufacturing complexity
Applied Scientific Principles
This section explains which scientific principles are used to turn an abstract innovation direction into a practical engineering solution.
Function Achieved in This Case
This approach reduces resistance and enhances the thermal stability of interconnect structures, addressing the RC delay issues in advanced semiconductor devices.
Implementation Method 1
a blocking layer to prevent metal diffusion
Implementation Method 2
an anneal process to enhance miscibility and stability
Data Source
AI summary
In some embodiments, an interconnect structure includes a first conductive structure disposed in a first dielectric layer, wherein the first conductive structure includes a first barrier layer and a first main conductive layer; a second dielectric layer disposed over the first dielectric layer; and a second conductive structure disposed in the second dielectric layer and over the first conductive structure, wherein the second conductive structure includes: a second barrier layer including a first conductive material selected from Ru or Mo; a second main conductive layer disposed over the second barrier layer and including a second conductive material; and a third conductive material being a dopant doped in the second main conductive layer or being a continuous layer between the second main conductive layer and the second barrier layer, wherein the third conductive material is selected from Mn, Ti, Co, Ru, Al, Zn, In, or combinations thereof.