Semiconductor Interconnect Barrier Layer Surface Modification
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Solution Overview
Problem
As semiconductor devices shrink, the formation and structure of interconnects become increasingly complex, leading to challenges in reducing the size of interconnects while minimizing defects and improving efficiency.
Innovation Solution
A surface modification process involving oxide reduction and surfactant soaking is used to selectively deposit a barrier layer on the sidewalls of openings, reducing the barrier layer deposition rate on the bottom surface, thereby minimizing the barrier layer within the interconnects and lowering contact resistance between conductive features.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Manufacturing precision
If conventional photolithographic, etching, deposition, and planarization techniques are used to form interconnections, then interconnects can be formed, but the process becomes increasingly complicated as device size is reduced
Solution Approach 1:
The patent applies preliminary action by performing surface modification (oxide reduction and surfactant soaking) on the conductive feature surface before barrier layer deposition. This pre-treatment modifies the surface properties to control subsequent barrier material deposition, enabling better deposition control at smaller interconnect dimensions without increasing overall process complexity
Solution Approach 2:
The patent changes physical and chemical parameters of the conductive feature surface through oxide reduction (changing oxidation state) and surfactant soaking (changing surface energy and wetting properties). These parameter changes enable selective barrier layer deposition with controlled thickness and distribution, achieving precise interconnect formation at reduced sizes
2Reliability
If barrier layer is deposited in openings to prevent diffusion, then diffusion barrier is provided, but contact resistance between conductive features increases
Solution Approach 1:
The patent applies local quality by creating non-uniform barrier layer distribution through surface modification. The surfactant soaking creates regions of different barrier material deposition rates, resulting in thinner barrier layers at critical contact regions while maintaining adequate barrier thickness in other areas. This provides both diffusion barrier reliability and low contact resistance
Solution Approach 2:
The patent uses partial action by applying surfactant treatment only to specific surfaces of conductive features where controlled barrier deposition is needed. This selective surface modification enables the barrier layer to be deposited with varying thicknesses in different locations, optimizing both diffusion prevention and electrical contact properties
Applied Scientific Principles
This section explains which scientific principles are used to turn an abstract innovation direction into a practical engineering solution.
Function Achieved in This Case
This approach effectively reduces the amount of barrier layer within interconnects, leading to lower contact resistance and improved efficiency in semiconductor device interconnect formation.
Implementation Method 1
performing a surfactant soaking process on the exposed surface of the conductive feature, the surfactant soaking process suppressing a deposition rate of a first barrier material of the first barrier layer over the exposed surface of the conductive feature
Implementation Method 2
performing an oxide reduction process on the exposed surface of the conductive feature
Data Source
AI summary
A semiconductor structure and a method of forming the same are provided. A method includes depositing a dielectric layer over a conductive feature. The dielectric layer is patterned to form an opening therein. The opening exposes a first portion of the conductive feature. A first barrier layer is deposited on a sidewall of the opening. The first portion of the conductive feature remains exposed at the end of depositing the first barrier layer.