Multi-chip Package Interconnect Bridge Devices for High-Density I/O
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Solution Overview
Problem
Conventional semiconductor packaging technologies, such as ceramic-based and organic laminate substrates, are limited in achieving high-density I/O flip-chip connections and die-to-die interconnections due to constraints in contact pad pitch, line width, and line spacing, which hinders the development of high-performance and high-density integrated package solutions.
Innovation Solution
The method involves fabricating multi-chip package structures by joining IC chips to pre-positioned interconnect bridge devices on a bridge wafer, with a wafer-level molding layer encapsulating the chips, and then releasing and dicing the interconnect bridge devices to form individual multi-chip modules, allowing for precise control of interconnect spacing and orientation.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Manufacturing precision
If conventional ceramic-based or organic laminate substrates are used for MCM packaging, then manufacturing is easier and cost is lower, but contact pad pitch, line width, and line spacing cannot achieve the tight pitches needed for high-density I/O flip-chip connections
Solution Approach 1:
The substrate is divided into multiple layers (first substrate layer, second substrate layer) with through-substrate vias connecting them. This segmentation allows each layer to be optimized independently for high-density interconnections while maintaining manufacturability through modular fabrication processes.
Solution Approach 2:
The patent transitions from planar interconnections to three-dimensional interconnections by stacking multiple substrate layers vertically and using through-substrate vias. This adds the vertical dimension to the interconnect architecture, enabling higher I/O density without increasing lateral complexity.
2Productivity
If higher I/O density and tighter pitch connections are achieved, then bandwidth and performance improve, but manufacturing precision requirements increase significantly
Solution Approach 1:
By segmenting the interconnect function across multiple substrate layers, each layer can use larger, more manufacturable line widths and spacings. The cumulative effect of multiple layers achieves the required total interconnect density without requiring individually impossibly small features.
Solution Approach 2:
The patent moves the density requirement from the lateral plane to the vertical dimension by stacking substrate layers. This allows achieving high I/O density through increased layer count rather than through increasingly difficult lateral miniaturization.
3Adaptability or versatility
If multi-layer ceramic or laminate substrates are used to provide die-to-die connections, then chip connectivity is enabled, but the substrates cannot support the tight pitches needed for high-density packaging
Solution Approach 1:
The connectivity function is segmented across multiple substrate layers, with each layer providing a subset of the required interconnections. This allows each layer to be designed with manufacturable pitch requirements while collectively supporting high-density chip connectivity.
Solution Approach 2:
The patent enables chip connectivity by adding vertical stacking of substrate layers, transforming the problem from two-dimensional high-density routing to a three-dimensional architecture where connectivity is achieved through the combination of lateral and vertical interconnections.
Data Source
AI summary
Techniques are provided for constructing multi-chip package structures using pre-positioned interconnect bridge devices that are fabricated on a bridge wafer. For example, integrated circuit chips are mounted to a bridge wafer which is formed to have a plurality of pre-positioned interconnect bridge devices, wherein at least two integrated circuit chips are joined to each interconnect bridge device, and wherein each interconnect bridge device includes wiring to provide chip-to-chip connections between the integrated circuit chips connected to the interconnect bridge device. A wafer-level molding layer is formed on the bridge wafer to encapsulate the integrated circuit chips mounted to the bridge wafer. The interconnect bridge devices are released from the bridge wafer. The wafer-level molding layer is then diced to form a plurality of individual multi-chip modules.