Semiconductor Interconnect Bridge Layout for Efficient Power Delivery
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Solution Overview
Problem
Internal connection circuitry in semiconductor packages can interfere with power delivery conductors, leading to inefficiencies and other issues due to extended wire runs, which reduce the overall circuit efficiency.
Innovation Solution
The use of an interconnect bridge with conductors configured to directly couple semiconductor dies through a redistribution layer, reducing the length of connections and minimizing interference with internal connection circuitry, and employing substrateless interconnect bridges with conductors arranged to carry power efficiently.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Adaptability or versatility
If internal connection circuitry is used to electrically connect multiple ICs within a package, then the ICs can be interconnected, but the connection circuit interferes with power delivery conductors and extends wire runs, reducing circuit efficiency
Solution Approach 1:
The patent introduces an interconnect bridge structure that extends vertically between upper and lower substrates, utilizing the third dimension (Z-axis) to establish direct electrical connections between ICs on different layers. This vertical interconnection path bypasses the need for extended lateral wire runs on a single substrate plane, thereby reducing resistance and improving power delivery efficiency while maintaining interconnection capability.
Solution Approach 2:
The interconnect bridge acts as an intermediary structure between the upper and lower substrates, providing dedicated vertical pathways for both signal and power connections. This mediator structure separates power delivery functions from signal routing functions, allowing power conductors to travel directly through the bridge without interference from internal connection circuitry on the substrate planes.
2Reliability
If extended wire runs are used for power delivery due to internal connection circuitry, then connections can be established between ICs, but resistive voltage drops and thermal losses increase
Solution Approach 1:
By transitioning from two-dimensional lateral wire routing on substrate planes to three-dimensional vertical routing through the interconnect bridge, the patent significantly shortens the physical path length for power delivery. This dimensional change reduces both the number of connection segments and the total wire length, thereby minimizing resistive voltage drops and thermal losses while ensuring reliable electrical connections between ICs.
3Device complexity
If internal connection circuitry is placed on the same substrate as power delivery conductors, then routing is simplified, but interference and efficiency losses occur
Solution Approach 1:
The patent segments the interconnection system into distinct functional layers: the upper substrate contains ICs and associated circuitry, the interconnect bridge provides vertical power and signal pathways, and the lower substrate contains additional ICs and circuitry. This segmentation separates power delivery conductors in the vertical bridge structure from lateral signal routing on the substrate planes, reducing electromagnetic interference and improving power delivery efficiency while maintaining manageable routing complexity through layered organization.
Applied Scientific Principles
This section explains which scientific principles are used to turn an abstract innovation direction into a practical engineering solution.
Function Achieved in This Case
This approach reduces resistive voltage drops and thermal losses, enhancing power delivery efficiency by minimizing the length of connections and optimizing the layout of conductors within the semiconductor package.
Implementation Method 1
the interconnect bridge comprising: a first plurality of conductors configured to electrically couple the plurality of connections of a first semiconductor die and the plurality of connections of a second semiconductor die
Implementation Method 2
reduces resistive voltage drops and thermal losses, enhancing power delivery efficiency
Data Source
AI summary
Embodiments of the present disclosure include techniques for a package and process for semiconductor dies. An interconnect bridge includes first conductors that electrically connect two or more semiconductor die. The interconnect bridge includes second conductors between opposite surfaces. A substrate of the interconnect bridge is removed to expose conductors of an interconnect layer that are electrically coupled to connections to the first and second semiconductor dies in a region of overlap between the semiconductor dies and interface bridge.