Interconnect Copper Migration Prevention

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Solution Overview

Problem

The challenge lies in assembling high-yielding non-volatile memory arrays that are fully integrated with surrounding logic circuitry using interconnect and metallization structures, particularly in preventing copper migration during the fabrication process which leads to electrical failures.

Innovation Solution

A conductive layer is selectively formed on the copper interconnect to prevent copper redistribution during sputtering, using materials that do not migrate, and ensuring the layer's thickness does not expose the copper interconnect, thus maintaining electrical connectivity and preventing copper migration.

Engineering Contradictions & Design Principles

VSEngineering Contradiction Analysis

1Reliability

If copper interconnect is used for electrical connectivity, then electrical conductivity is improved, but copper migration occurs during sputtering causing electrical failures

Engineering Contradiction:
Improveelectrical connectivityVSAvoidcopper migration
Core Design Contradiction:
ReliabilityVSObject-generated harmful factors

Solution Approach 1:

A non-migrating conductive layer is introduced as an intermediary between the copper interconnect and the dielectric layer. This intermediate layer prevents copper atoms from migrating during sputtering processes while maintaining electrical conductivity, thus resolving the contradiction between reliable electrical connectivity and copper migration prevention.

Inventive Principle:
Principle #24Intermediary (Mediator)

Solution Approach 2:

The conductive layer is designed to serve dual functions: it provides electrical conductivity like copper while simultaneously protecting the copper interconnect from migration during subsequent fabrication steps. The layer essentially protects itself and the underlying copper structure from the harmful effects of sputtering.

Inventive Principle:
Principle #25Self-service

2Object-generated harmful factors

If a protective layer is added to prevent copper migration, then copper migration is reduced, but device complexity increases

Engineering Contradiction:
Improvecopper migrationVSAvoidinterconnect structure
Core Design Contradiction:
Object-generated harmful factorsVSDevice complexity

Solution Approach 1:

The conductive layer uses materials with altered physical and chemical parameters compared to traditional copper-only interconnects. By selecting materials with appropriate conductivity, migration resistance, and thickness parameters, the layer prevents copper migration while maintaining compatibility with existing interconnect architectures, thus minimizing the increase in device complexity.

Inventive Principle:
Principle #35Parameter changes

3Productivity

If feature size is reduced for higher density, then manufacturing cost is reduced and density is improved, but copper migration becomes more severe

Engineering Contradiction:
Improvechip densityVSAvoidcopper migration
Core Design Contradiction:
ProductivityVSObject-generated harmful factors

Solution Approach 1:

The non-migrating conductive layer is formed as a preliminary protective barrier before subsequent sputtering steps are performed. This pre-established protection ensures that even as feature sizes are reduced for higher density, the copper interconnect remains protected from migration, allowing continued scaling without exacerbating the copper migration problem.

Inventive Principle:
Principle #10Preliminary action

Applied Scientific Principles

This section explains which scientific principles are used to turn an abstract innovation direction into a practical engineering solution.

Function Achieved in This Case

This approach effectively mitigates copper migration, ensuring robust electrical connectivity and preventing electrical failures during the fabrication of non-volatile memory arrays integrated with logic circuitry.

Implementation Method 1

prevent copper redistribution during sputtering

Methodology Applied
Scientific EffectSputtering: Sputtering

Data Source

PatentUS11430944B2Interconnect structures for logic and memory devices and methods of fabrication
Publication Date: 2022.08.30 INTEL CORP
  • US11430944B2 patent drawing
  • US11430944B2 patent drawing
  • US11430944B2 patent drawing

AI summary

An apparatus includes a first interconnect structure above a substrate, a memory device above and coupled with the first interconnect structure in a memory region. The memory device includes a non-volatile memory element, an electrode on the non-volatile memory element, and a metallization structure on a portion of the electrode. The apparatus further includes a second interconnect structure in a logic region above the substrate, where the second interconnect structure is laterally distant from the first interconnect structure. The logic region further includes a second metallization structure coupled to the second interconnect structure and a conductive structure between the second metallization structure and the second interconnect structure. The apparatus further includes a dielectric spacer that extends from the memory device to the conductive structure.