Interconnect Isolation Structure for Tight Dielectric Spacing

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Solution Overview

Problem

The challenge in semiconductor manufacturing lies in shrinking the critical dimension of dielectric spacing between interconnect structures in ICs, as existing methods face issues with peeling or shifting during patterning, leading to increased contact resistances and fabrication complexities, especially in core areas like SRAM.

Innovation Solution

A damascene-like process is employed to form an isolation structure by recessing an interlayer dielectric and filling it with a dielectric material, avoiding the formation of island-like patterns and mitigating lithography limitations, thus enhancing the length of interconnect structures.

Engineering Contradictions & Design Principles

VSEngineering Contradiction Analysis

1Length of moving object

If the critical dimension of dielectric spacing is reduced to increase interconnect length, then the contact resistance increases and patterning reliability deteriorates due to peeling or shifting

Engineering Contradiction:

Improveinterconnect lengthVSAvoidpatterning precision

Core Design Contradiction:

Length of moving objectVSManufacturing precision

Solution Approach 1:

Instead of directly patterning the dielectric spacing between interconnect structures, the patent inverts the approach by first forming the interconnect structures and then defining the dielectric spacing as the remaining material between them. This reverse patterning approach eliminates the peeling and shifting issues associated with direct patterning of narrow dielectric spaces.

Inventive Principle:

Principle #13The other way round (Inversion)

Solution Approach 2:

The patent performs preliminary actions by forming the interconnect structures and their surrounding dielectric material before finally defining the precise dielectric spacing. The dielectric material is deposited and planarized in advance, and only the interconnect structures are selectively removed or patterned, ensuring that the dielectric spacing is established without direct patterning stress.

Inventive Principle:

Principle #10Preliminary action

2Length of moving object

If the critical dimension of dielectric spacing is reduced to enhance interconnect length, then fabrication complexity increases due to lithography limitations

Engineering Contradiction:

Improveinterconnect lengthVSAvoidfabrication complexity

Core Design Contradiction:

Length of moving objectVSDevice complexity

Solution Approach 1:

The patent transitions from two-dimensional planar patterning to a three-dimensional approach by forming interconnect structures with vertical depth and then defining dielectric spacing in the lateral dimension. This dimensional change allows the dielectric spacing to be controlled by the interconnect structure geometry rather than direct lithographic patterning, bypassing lithography resolution limits.

Inventive Principle:

Principle #17Another dimension (Dimensionality change)

Solution Approach 2:

The interconnect structures serve as intermediary elements that indirectly define the dielectric spacing. Instead of directly patterning the dielectric material to create spacing, the interconnect structures are formed first and act as templates or mediators that automatically establish the required dielectric spacing between them, simplifying the fabrication process.

Inventive Principle:

Principle #24Intermediary (Mediator)

3Manufacturing precision

If conventional patterning methods are used to reduce dielectric spacing, then contact resistance increases due to peeling or shifting

Engineering Contradiction:

Improvedielectric spacing controlVSAvoidcontact resistance

Core Design Contradiction:

Manufacturing precisionVSReliability

Solution Approach 1:

The patent inverts the conventional patterning sequence by forming the interconnect structures and their supporting dielectric material first, then defining the precise dielectric spacing as the remaining material between the interconnect structures. This eliminates the mechanical stress and peeling issues that occur when directly patterning narrow dielectric spaces, thereby maintaining low contact resistance.

Inventive Principle:

Principle #13The other way round (Inversion)

Solution Approach 2:

The dielectric material is deposited and planarized in advance before the interconnect structures are finalized. This preliminary formation of the dielectric layer ensures that when the dielectric spacing is later defined, the material is already stable and properly adhered, preventing peeling and shifting that would increase contact resistance.

Inventive Principle:

Principle #10Preliminary action

Data Source

PatentUS12142532B2Interconnect structures for semiconductor devices and methods of manufacturing the same

Publication Date: 2024.11.12 TAIWAN SEMICONDUCTOR MANUFACTURING CO LTD

AI summary

A semiconductor device includes a first source/drain structure coupled to an end of a first conduction channel that extends along a first direction. The semiconductor device includes a second source/drain structure coupled to an end of a second conduction channel that extends along the first direction. The semiconductor device includes a first interconnect structure extending through an interlayer dielectric and electrically coupled to the first source/drain structure. The semiconductor device includes a second interconnect structure extending through the interlayer dielectric and electrically coupled to the second source/drain structure. The semiconductor device includes a first isolation structure disposed between the first and second source/drain structures and extending into the interlayer dielectric.