Interconnect Wire Protection Liner for Precise Via Formation
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Solution Overview
Problem
As semiconductor integrated circuits (ICs) shrink in size, the increased spacing between conductive features leads to higher capacitance, power consumption, and time delays, which existing manufacturing techniques struggle to address due to limitations in photolithography and etching precision.
Innovation Solution
The use of a protection liner, such as graphene, on interconnect wires to prevent the formation of interconnect vias below the liner, maintaining isolation and reducing electron scattering, thereby enhancing processing precision and reliability.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Manufacturing precision
If photolithography and etching precision are improved to reduce spacing between conductive features, then manufacturing precision is improved, but device complexity and process difficulty increase due to physical limitations
Solution Approach 1:
A protection liner is formed on the interconnect wire before via formation to prevent etch damage to the dielectric layer. This preliminary protective action enables more aggressive via etching processes without compromising the underlying dielectric structure, effectively decoupling the via formation process from the dielectric layer integrity constraints.
Solution Approach 2:
The protection liner acts as an intermediary layer between the etch process and the dielectric layer. This intermediate structure absorbs the harsh etching conditions, allowing precise via formation while protecting the sensitive dielectric layer from damage, thus enabling reduced spacing without increasing process complexity.
2Productivity
If spacing between conductive features is reduced to increase density, then productivity is improved, but capacitance increases leading to higher power consumption and time delay
Solution Approach 1:
The protection liner is formed in advance to enable precise via formation at reduced spacing. This allows the circuit design to achieve higher density by placing conductive features closer together, while the protected via formation process ensures electrical integrity is maintained, preventing energy loss from manufacturing defects.
3Productivity
If interconnect vias are formed closer to interconnect wires to increase density, then productivity is improved, but manufacturing precision deteriorates due to difficulty in preventing via formation below the wire
Solution Approach 1:
The protection liner is deposited on the interconnect wire surface before via formation. This preliminary protective layer creates a physical barrier that prevents the etch process from forming vias below the wire level, enabling higher interconnect density while maintaining precise via placement through the liner's protective function.
Solution Approach 2:
The protection liner serves as an intermediary structure that mediates between the via etch process and the interconnect wire. It allows the via to be formed close to the wire while preventing unwanted etching below the wire, thus enabling high density interconnect design without sacrificing manufacturing precision.
4Reliability
If protection liner is added to prevent via formation below wire, then reliability is improved, but device complexity increases due to additional processing steps
Solution Approach 1:
The protection liner serves multiple functions: it protects the dielectric layer from etch damage, prevents via formation below the wire, and maintains the topography for subsequent processing steps. This multi-functionality justifies the additional processing step by providing comprehensive protection and enabling higher density designs.
Solution Approach 2:
The protection liner is formed as a preliminary step to prevent multiple potential failures: dielectric layer damage, via misalignment, and electrical integrity issues. This single preliminary action addresses multiple reliability concerns that would otherwise require additional complex process steps.
Applied Scientific Principles
This section explains which scientific principles are used to turn an abstract innovation direction into a practical engineering solution.
Function Achieved in This Case
The protection liner increases the processing window for forming interconnect vias, reduces capacitance, and maintains electrical integrity by preventing damage to dielectric layers and air spacer structures, thus improving the reliability and efficiency of the integrated circuits.
Implementation Method 1
reducing electron scattering, thereby enhancing processing precision and reliability
Data Source
AI summary
In some embodiments, the present disclosure relates an integrated chip including a substrate. A conductive interconnect feature is arranged over the substrate. The conductive interconnect feature has a base feature portion with a base feature width and an upper feature portion with an upper feature width. The upper feature width is narrower than the base feature width such that the conductive interconnect feature has tapered outer feature sidewalls. An interconnect via is arranged over the conductive interconnect feature. The interconnect via has a base via portion with a base via width and an upper via portion with an upper via width. The upper via width is wider than the base via width such that the interconnect via has tapered outer via sidewalls.