Interconnect Modeling via Local Distant Wire Variation

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Solution Overview

Problem

Existing methods for modeling interconnect structures in integrated circuits often fail to accurately reflect the electrical characteristics of real-world designs due to inconsistencies in wire variations, leading to flawed verification results and potential design failures.

Innovation Solution

A test structure is designed with intentional variations in physical properties between local and distant interconnects, allowing for more accurate modeling of electrical properties by measuring and accounting for these variations, which are then used to create interconnect models for improved IC design and verification.

Engineering Contradictions & Design Principles

VSEngineering Contradiction Analysis

1Ease of manufacture

If a test structure with consistent wire array is used for modeling, then the modeling process is simplified, but the accuracy of electrical characteristics prediction deteriorates

Engineering Contradiction:
Improvemodeling process simplicityVSAvoidelectrical characteristics prediction accuracy
Core Design Contradiction:
Ease of manufactureVSMeasurement precision

Solution Approach 1:

The patent applies local quality by creating different wire structure configurations in different regions of the test chip. Local interconnects have one physical configuration while distant interconnects have different physical configurations, allowing each region to provide specific measurement data for different modeling scenarios. This resolves the contradiction by maintaining measurement accuracy across varying wire configurations while keeping the overall test structure manufacturable using standard fabrication processes.

Inventive Principle:
Principle #3Local quality

2Device complexity

If wire variations between local and distant interconnects are ignored, then the test structure design is simplified, but the reliability of IC design verification deteriorates

Engineering Contradiction:
Improvetest structure design complexityVSAvoidIC design verification reliability
Core Design Contradiction:
Device complexityVSReliability

Solution Approach 1:

The patent segments the test structure into distinct local and distant interconnect regions with different wire configurations. This segmentation allows the test structure to capture a broader range of real-world wire variations while maintaining a systematic and manageable design. By dividing the test structure into functional segments, the patent improves verification reliability without excessively increasing design complexity.

Inventive Principle:
Principle #1Segmentation

Solution Approach 2:

The patent deliberately changes physical parameters (wire width, spacing, length) between local and distant interconnects to reflect real-world variations. This parameter variation enables more reliable modeling and verification by accounting for different electrical characteristics that would occur in actual IC designs, thereby improving verification reliability while maintaining reasonable design complexity.

Inventive Principle:
Principle #35Parameter changes

3Ease of manufacture

If real-world wire variations are not accounted for in test structures, then the test structure fabrication is easier, but the accuracy of electrical model predictions deteriorates

Engineering Contradiction:
Improvetest structure fabrication easeVSAvoidelectrical model prediction accuracy
Core Design Contradiction:
Ease of manufactureVSMeasurement precision

Solution Approach 1:

The patent implements local quality by designing specific wire configurations in local versus distant regions of the test structure. This approach captures real-world wire variations that affect electrical characteristics while still using standard fabrication processes. The different local configurations reflect actual IC design variations without requiring complex or non-standard manufacturing, thus resolving the contradiction between fabrication ease and prediction accuracy.

Inventive Principle:
Principle #3Local quality

Data Source

PatentUS7653519B1Method and mechanism for modeling interconnect structures for integrated circuits
Publication Date: 2010.01.26 CADENCE DESIGN SYST INC
  • US7653519B1 patent drawing
  • US7653519B1 patent drawing
  • US7653519B1 patent drawing

AI summary

Disclosed are methods, systems, and structures for implementing interconnect modeling by using a test structure which include a variation of physical wire structures between local interconnects and distant interconnects. According to one approach, the impact of variations of the physical properties for neighborhood wires are considered for the electrical modeling of interconnects. This variation between the local and distant wire characteristics allows more accurate and robust interconnect modeling to be created.