Interconnect Structure Seed Layer Undercutting Prevention
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Solution Overview
Problem
The existing semiconductor manufacturing processes face challenges in forming interconnect structures, such as conductive pillars, over a seed layer on a contact pad without undercutting the seed layer, which leads to adhesion issues and manufacturing reliability problems due to the inability to precisely control the wet etch rate and high current density around the interconnects.
Innovation Solution
A method is developed to form interconnect structures with a first width within the opening of an insulating layer and a second width less than the opening outside the insulating layer, preventing undercutting of the seed layer and maintaining adhesion by controlling the etch stop at the edge of the insulating layer, thereby reducing stress on the insulating layer and increasing manufacturing reliability.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Manufacturing precision
If wet etching process is used to remove seed layer outside conductive pillar footprint, then seed layer can be removed from areas outside interconnect structure, but wet etch undercuts and removes portion of seed layer beneath conductive pillars causing adhesion weakness
Solution Approach 1:
A barrier layer is deposited over the seed layer before forming the conductive pillar. This preliminary action creates a protective interface that prevents the wet etch from undercutting the seed layer beneath the conductive pillar, while still allowing selective removal of seed layer outside the pillar footprint through the opening in the insulating layer.
Solution Approach 2:
The barrier layer acts as an intermediary between the wet etch process and the seed layer. It mediates the etching process by being selectively removed in controlled areas (outside the conductive pillar footprint) while protecting the seed layer underneath the pillar from undercutting, thus enabling precise seed layer removal without compromising adhesion.
2Productivity
If smaller interconnect pitch is used to increase routing density, then higher interconnect and routing density is achieved, but wet etch undercutting occurs more frequently due to inability to precisely control etch rate
Solution Approach 1:
The barrier layer is deposited in advance before the conductive pillar formation and wet etching processes. This preliminary protective layer enables the use of smaller interconnect pitches by providing a buffer that prevents etch undercutting, allowing higher routing density without sacrificing manufacturing precision even when etch rate control is challenging.
3Area of stationary object
If conductive pillar is formed up to edge of insulating layer to maximize space utilization, then space efficiency is improved, but high current density exists around base of conductive pillars adjacent to insulating layer increasing interconnect resistance
Solution Approach 1:
The solution creates different local structures: within the opening, the conductive pillar is formed up to the edge of the insulating layer for space efficiency, but outside the opening, the barrier layer extends beyond the insulating layer edge to provide a wider conductive path. This local quality variation reduces current density at the critical interface region while maintaining space utilization inside the opening.
Applied Scientific Principles
This section explains which scientific principles are used to turn an abstract innovation direction into a practical engineering solution.
Function Achieved in This Case
This approach enhances the adhesion between interconnect structures and the contact pads, reduces the occurrence of joint cracking, and improves the reliability of semiconductor devices by maintaining the seed layer integrity and reducing interconnect resistance.
Implementation Method 1
The wet etch is known to remove a portion of the seed layer under the conductive pillars, i.e., the wet etch undercuts the seed layer beneath the conductive pillars.
Data Source
AI summary
A semiconductor device has a semiconductor die with a first conductive layer formed over the die. A first insulating layer is formed over the die with a first opening in the first insulating layer disposed over the first conductive layer. A second conductive layer is formed over the first insulating layer and into the first opening over the first conductive layer. An interconnect structure is constructed by forming a second insulating layer over the first insulating layer with a second opening having a width less than the first opening and depositing a conductive material into the second opening. The interconnect structure can be a conductive pillar or conductive pad. The interconnect structure has a width less than a width of the first opening. The second conductive layer over the first insulating layer outside the first opening is removed while leaving the second conductive layer under the interconnect structure.


