Metal Interconnect Sidewall Spacers for Low-RC Chip Wiring
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Solution Overview
Problem
As device dimensions shrink, increased line resistance and parasitic capacitance lead to slower chip speeds and higher power consumption, and the use of air gaps between interconnect lines is hindered by reduced mechanical strength and structural deformation in integrated circuits.
Innovation Solution
A method involving the formation of spacers on the sidewalls of metal interconnections, followed by the creation of additional metal interconnections that land on both the original interconnections and the spacers, effectively reducing capacitance while maintaining structural integrity by using a low-k dielectric material and air gaps.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Loss of time
If air gaps are formed between interconnect lines to reduce dielectric constant, then RC signal delay is reduced and chip performance is improved, but mechanical strength is reduced and structural deformation occurs
Solution Approach 1:
The patent introduces spacers as intermediary structures between the metal interconnect lines. These spacers fill the air gaps and provide mechanical support while allowing the beneficial low-k dielectric environment to persist. The spacers act as a mediator that enables both the air gap structure (for low RC delay) and mechanical strength requirements to coexist.
Solution Approach 2:
The patent creates a composite interconnect structure combining metal interconnect lines, low-k dielectric materials, and spacer structures. This composite approach allows the system to leverage the low dielectric constant of air-gap structures while the spacers provide the necessary mechanical reinforcement, achieving both electrical performance and structural integrity.
2Productivity
If spacing between conducting lines is reduced to increase packing density, then more interconnections can be formed, but parasitic capacitance increases and RC signal delay worsens
Solution Approach 1:
The patent applies local quality by creating different dielectric environments in different regions. The air gaps and spacers are strategically placed in specific locations between interconnect lines to locally reduce the dielectric constant where it matters most for capacitance reduction, while maintaining close spacing overall for high packing density.
Data Source
AI summary
A method for fabricating semiconductor device includes the steps of: forming a first inter-metal dielectric (IMD) layer on a substrate; forming a first metal interconnection in the first IMD layer; removing part of the first IMD layer; forming a spacer adjacent to the first metal interconnection; forming a second IMD layer on the spacer and the first metal interconnection; and forming a second metal interconnection in the second IMD layer and on the spacer and the first metal interconnection.