Interconnect Sidewall Spacer Structure for Via Misalignment Isolation
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Solution Overview
Problem
The existing interconnect structures in semiconductor devices face challenges with misalignment and degradation of isolation characteristics due to misaligned via holes and trenches, leading to potential short-circuits and discontinuity in current flow, particularly when using copper and ruthenium metal patterns.
Innovation Solution
The implementation of a spacer structure on the sidewalls of metal patterns and vias, formed from a dielectric material with a higher dielectric constant than the ILD layer, which provides etch selectivity and protects the ILD layer from misalignment-related damage, maintaining isolation characteristics and reducing short-circuit risks.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Reliability
If a barrier metal layer is added to prevent copper diffusion into the ILD layer, then isolation properties are improved, but the area occupied by the metal pattern is reduced, affecting conduction capability
Solution Approach 1:
The patent introduces a spacer structure as an intermediary element formed on the sidewalls of metal patterns and vias. This spacer acts as a protective mediator that prevents etch damage to the ILD layer during misalignment, eliminating the need for a barrier metal layer while maintaining both isolation properties and metal pattern area for conduction.
2Ease of manufacture
If via holes and trenches are formed without precise alignment, then manufacturing complexity is reduced, but isolation characteristics deteriorate due to unintended grooves and short-circuits
Solution Approach 1:
The spacer structure serves as a pre-formed protective cushion on the sidewalls of metal patterns and vias. This beforehand protection absorbs the impact of misalignment during etching, preventing unintended groove formation and maintaining isolation characteristics even when via holes and trenches are not precisely aligned.
3Manufacturing precision
If the dielectric material of the spacer structure has a higher dielectric constant than the ILD layer, then etch selectivity is improved, but the isolation space margin is reduced
Solution Approach 1:
The patent utilizes parameter changes in dielectric constant to achieve etch selectivity. By selecting a dielectric material with a higher dielectric constant than the ILD layer, the spacer structure becomes etch-resistant during misalignment, allowing precise control of etching depth while maintaining adequate isolation space margins.
Data Source
Figure 1A~1B
Figure 2A~2B
Figure 3A~3B
AI summary
Provided is a semiconductor device including at least one front-end-of-line, FEOL, element connected to an interconnect structure, the interconnect structure including: a 1st metal pattern or via structure with a spacer structure on a sidewall thereof; and a 1st interlayer dielectric, ILD, layer formed at sides of the 1st metal pattern or via structure with the spacer structure on the sidewall thereof, wherein the spacer structure includes a dielectric material different from a material included in the 1st ILD layer.