Multi-Level Interconnect Structure Trench Via Formation
Find Innovative SolutionsGenerate Solutions
Solution Overview
Problem
Traditional methods for forming multi-level interconnect structures in semiconductor devices result in chamfered edges between vias and trenches, leading to increased critical dimension variability and risk of dielectric breakdown.
Innovation Solution
The method involves forming a trench before vias and multi-level vias, with sacrificial materials in the trench to protect the interface, and subsequent removal and deposition of conductive materials to reduce chamfering and improve structural integrity.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Ease of manufacture
If traditional dual-damascene patterning and partial etching of supervia and via are performed, then the multi-level interconnect structure can be formed, but chamfered edges are formed at the interface between vias and trench
Solution Approach 1:
The patent applies preliminary action by performing a shallow etch of the trench before forming the vias and multi-level vias. This pre-etching step creates a modified trench profile that prevents chamfering during subsequent via etching, thereby maintaining critical dimension control while still enabling multi-level interconnect structure formation.
Solution Approach 2:
The patent segments the trench formation process from the via formation process. By separately etching the trench to a controlled depth first, then subsequently forming vias that extend through the trench, the method isolates the trench interface from the via etching process, preventing the formation of chamfered edges at the interface.
2Productivity
If traditional complete etch of supervia and via along with trench in a single step is performed, then the multi-level interconnect structure can be formed, but the distance between patterned features is reduced
Solution Approach 1:
The patent segments the etching process into distinct steps: first etching the trench to a controlled shallow depth, then separately etching the vias and multi-level vias. This segmentation allows independent control of trench depth and via dimensions, preventing the reduction of feature spacing that occurs in single-step complete etching while maintaining overall process efficiency.
Solution Approach 2:
The patent performs preliminary trench etching before via etching. This preliminary action establishes the trench boundaries and depth control before the via formation process begins, ensuring that the distance between patterned features is maintained while still achieving complete multi-level interconnect formation.
3Ease of manufacture
If chamfered edges are formed at the interface between vias and trench, then the multi-level interconnect structure can be formed, but via resistance variability increases
Solution Approach 1:
The patent performs preliminary trench etching to a controlled shallow depth before forming vias. This preliminary action creates a trench profile with controlled walls that prevent chamfering during subsequent via etching, thereby maintaining consistent via dimensions and reducing via resistance variability while still enabling interconnect structure formation.
Solution Approach 2:
The patent segments the formation process to separate trench creation from via creation. By controlling the trench depth and profile independently before via formation, the method eliminates the chamfering effect that causes via resistance variability, ensuring reliable and consistent electrical properties.
Data Source
Figure 1~2
Figure 3~4
Figure 5~6
AI summary
According to an aspect of the present inventive concept there is provided a method for forming a multi-level interconnect structure in a semiconductor device comprising: a first interconnection level (110) including a first dielectric layer (112) and a first conductive structure (114); a second interconnection level (120) arranged above the first interconnection level (110) and including a second dielectric layer (122) and a second conductive structure (124); a third interconnection level (130) arranged above the second interconnection level (120) and including a third dielectric layer (132) and a third conductive structure (134); wherein the method comprises: forming a trench in the third dielectric layer; providing a first sacrificial material in the trench; and thereafter forming a via extending through the third interconnection level to the second conductive structure; providing a second sacrificial material in the via; forming a multi-level via extending through the third interconnection level to the first conductive structure; removing the first sacrificial material; removing the second sacrificial material; depositing a conductive material at least partially filling: the trench, thereby forming the third conductive structure (134); the via, thereby forming a via structure (102) forming an electrical connection between the third conductive structure (134) and the second conductive structure (124); and the multi-level via, thereby forming a multi-level via structure (104) forming an electrical connection between the third conductive structure (134) and the first conductive structure (114).