Interconnect Substrate Via Processing to Prevent Desmear Cracks

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Solution Overview

Problem

The formation of via holes in insulating layers of interconnect substrates using laser processing leads to thermal stress, which can cause cracks and resinous residues, resulting in conduction failures during the formation of additional interconnect layers.

Innovation Solution

A method involving a heat treatment, plasma processing, and a desmear process is applied to the insulating layer after forming via holes, followed by the formation of a second interconnect layer, utilizing a filler-rich insulating layer to reduce thermal stress and resinous residues.

Engineering Contradictions & Design Principles

VSEngineering Contradiction Analysis

1Reliability

If a desmear process is performed to remove resinous residue from via holes, then conduction reliability is improved, but cracks may occur in the insulating layer around via holes due to stress release

Engineering Contradiction:
Improveconduction reliabilityVSAvoidinsulating layer integrity
Core Design Contradiction:
ReliabilityVSStrength

Solution Approach 1:

The patent applies a preliminary stress relief process before the desmear process to remove thermal stress from the insulating layer. This preliminary action prevents cracks from occurring during the subsequent desmear process, allowing resinous residue removal without compromising insulating layer integrity.

Inventive Principle:
Principle #10Preliminary action

Solution Approach 2:

The patent converts the harmful thermal stress generated during laser via hole formation into a beneficial pre-condition by intentionally applying controlled stress relief treatment. This transforms the potential cause of cracks into a preparatory step that enables safe removal of resinous residue.

Inventive Principle:
Principle #22Blessing in disguise (Convert harm into benefit)

2Manufacturing precision

If laser processing is used to form via holes, then manufacturing precision is improved, but thermal stress remains in the insulating layer causing potential cracks

Engineering Contradiction:
Improvevia hole formation precisionVSAvoidthermal stress in insulating layer
Core Design Contradiction:
Manufacturing precisionVSStress or pressure

Solution Approach 1:

The patent acknowledges the thermal stress as an inevitable byproduct of laser processing but converts this harmful effect into a manageable condition by applying controlled stress relief treatment, thereby maintaining the manufacturing precision benefits of laser processing while eliminating the crack risk.

Inventive Principle:
Principle #22Blessing in disguise (Convert harm into benefit)

Solution Approach 2:

The patent introduces a stress relief process as an intermediary step between laser via hole formation and the desmear process. This intermediary treatment removes thermal stress from the insulating layer, acting as a mediator that allows the high-precision laser process to be followed by stress-sensitive operations without causing damage.

Inventive Principle:
Principle #24Intermediary (Mediator)

3Reliability

If multiple processing steps (heat treatment, plasma processing, desmear process) are performed in sequence, then insulating layer quality is improved, but manufacturing complexity increases

Engineering Contradiction:
Improveinsulating layer qualityVSAvoidprocessing sequence complexity
Core Design Contradiction:
ReliabilityVSDevice complexity

Solution Approach 1:

The patent segments the overall processing into distinct sequential steps (heat treatment → plasma processing → desmear process), where each step performs a specific function. This segmentation allows for optimized control of each individual process while achieving cumulative quality improvement in the insulating layer.

Inventive Principle:
Principle #1Segmentation

Solution Approach 2:

The patent utilizes parameter changes in each processing step (temperature in heat treatment, plasma conditions, chemical composition in desmear process) to progressively modify the insulating layer properties. By changing parameters systematically across steps, the patent achieves quality improvement through controlled transformations rather than complex mechanical interventions.

Inventive Principle:
Principle #35Parameter changes

Applied Scientific Principles

This section explains which scientific principles are used to turn an abstract innovation direction into a practical engineering solution.

Function Achieved in This Case

This method effectively reduces the likelihood of cracks in the insulating layer around via holes, enhancing the adhesion and reliability of the interconnect substrate by ensuring uniform surface roughness and peel strength.

Implementation Method 1

performing a heat treatment, plasma processing, and a desmear process in this order with respect to the first insulating layer

Methodology Applied
Scientific EffectThermal stress reduction: Heat Treatment

Implementation Method 2

performing a heat treatment, plasma processing, and a desmear process in this order with respect to the first insulating layer

Methodology Applied
Scientific EffectPlasma processing: Plasma

Implementation Method 3

forming a via hole in the first insulating layer by laser processing

Methodology Applied
Scientific EffectLaser ablation: Laser Ablation

Data Source

PatentUS12604395B2Method of making an interconnect substrate
Publication Date: 2026.04.14 SHINKO ELECTRIC IND CO LTD
  • US12604395B2 patent drawing
  • US12604395B2 patent drawing
  • US12604395B2 patent drawing

AI summary

A method of making an interconnect substrate includes forming a first insulating layer containing a filler and covering a first interconnect layer, forming a via hole in the first insulating layer by laser processing, the via hole exposing the first interconnect layer, performing a heat treatment, plasma processing, and a desmear process in this order with respect to the first insulating layer, and forming, after the desmear process, a second interconnect layer including both an interconnect pattern formed on an upper surface of the first insulating layer and a via interconnect formed in the via hole.