Interconnected Leads for Semiconductor Package Parasitic Reduction
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Solution Overview
Problem
Ceramic semiconductor packages face challenges in reducing electrical parasitics such as inductance and resistance due to lead design, which can lead to thermal stresses and attachment issues, and existing solutions like widening leads or increasing lead count compromise thermal conductivity and package size.
Innovation Solution
The introduction of interconnected leads with an interconnection portion between top and bottom portions, made from materials like iron, nickel, or their alloys, which are brazed to contact pads and circuit boards, reducing parasitics through additional metal length while allowing standard fabrication and assembly methods.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Object-generated harmful factors
If leads are widened to reduce electrical parasitics, then electrical parasitics are reduced, but lateral thermal stresses increase causing lead buckling or attachment failure
Solution Approach 1:
The lead is segmented into multiple portions with different cross-sectional areas. The upper portion has a larger cross-sectional area to reduce electrical parasitics, while the lower portion has a smaller cross-sectional area to reduce thermal stress and prevent buckling. This segmentation allows each portion to be optimized for its specific function.
Solution Approach 2:
Different portions of the lead have different local qualities in terms of cross-sectional area. The upper portion near the contact pad has a larger area for electrical performance, while the lower portion near the PCB has a smaller area for mechanical stability. This local quality variation resolves the contradiction between electrical and mechanical requirements.
2Object-generated harmful factors
If lead count is increased to reduce electrical parasitics, then electrical parasitics are reduced, but package footprint size increases
Solution Approach 1:
Instead of increasing the number of leads (one dimension), the invention changes the cross-sectional area dimension of existing leads. By varying the cross-sectional area along the lead length, electrical parasitics are reduced without adding more leads or increasing package footprint.
3Object-generated harmful factors
If leads are widened to reduce electrical parasitics, then electrical parasitics are reduced, but non-standard fabrication and assembly methods are required
Solution Approach 1:
The lead frame is designed with pre-formed varying cross-sectional areas during the standard fabrication process. This preliminary action allows the leads to have optimized electrical characteristics while still using standard fabrication and assembly methods, avoiding the need for post-fabrication modifications.
Applied Scientific Principles
This section explains which scientific principles are used to turn an abstract innovation direction into a practical engineering solution.
Function Achieved in This Case
This solution effectively reduces electrical parasitics, allows for stress relief at attachment points, and maintains thermal conductivity, enabling cost-efficient and reliable connections without compromising package size or thermal performance.
Implementation Method 1
Each of a second plurality of leads includes a top portion and a bottom portion and an interconnection portion between the top portion and the bottom portion. The top portion of each of the second plurality of leads includes separate finger portions that are electrically connected to at least two of the plurality of contact pads.
Implementation Method 2
made from materials like iron, nickel, or their alloys, which are brazed to contact pads and circuit boards
Implementation Method 3
If dissipation of heat and sealing of the semiconductor device within the package are critical to the operation of the semiconductor device, a ceramic package may be desired. Packaging materials in the ceramic package provide good thermal conductivity and hermeticity.
Data Source
AI summary
A semiconductor package includes a semiconductor die and a ceramic package body covering the semiconductor die. The ceramic package body includes a plurality of contact pads. Each of a first plurality of leads includes a top portion and a bottom portion. The top portion of each of the first plurality of leads is electrically connected to a contact pad of the plurality of contact pads. Each of a second plurality of leads includes a top portion and a bottom portion and an interconnection portion between the top portion and the bottom portion. The top portion of each of the second plurality of leads includes separate finger portions that are electrically connected to at least two of the plurality of contact pads.