Interconnection Device Loop Inductance Reduction
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Solution Overview
Problem
High parasitic inductance in electrical interconnection devices limits the fast switching properties of electronic components, causing overvoltages and oscillations.
Innovation Solution
The introduction of a second electrically conductive layer and an additional current flow plane perpendicular to the first, with an electrical connection between the two planes, reduces the inductance of the current circulation loop, allowing current to flow through both planes with opposite directions, thereby decreasing mutual inductance and overall inductance.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Device complexity
If a single current flow plane is used in the interconnection device, then the structure is simple and manufacturing is easier, but the loop inductance is high (greater than or equal to 30 nH) which prevents fast switching
Solution Approach 1:
The patent transitions from a single 2D current flow plane to a three-dimensional multi-plane structure. A second conductive layer is added below the first insulating substrate, creating a second current flow plane that is substantially parallel to and offset from the first plane. This dimensional expansion allows current to flow through multiple planes simultaneously in opposite directions, reducing the net loop inductance from ≥30 nH to <10 nH while maintaining structural integrity through insulating substrates and connection plates.
2Reliability
If multiple parallel circulation planes are introduced to reduce inductance, then switching speed improves, but the device complexity and manufacturing difficulty increase
Solution Approach 1:
The patent segments the current flow path into distinct parallel planes separated by insulating substrates. The first conductive layer forms a first circulation plane, while the second conductive layer forms a second circulation plane. These segmented planes are electrically connected through connection plates that pass through the insulating substrates, allowing independent optimization of each plane's current path while maintaining overall structural organization and facilitating manufacturing.
3Reliability
If the second conductive layer is made as a transpose of the first layer, then the inductance reduction is maximized through opposite current directions, but manufacturing precision requirements increase
Solution Approach 1:
The patent employs asymmetric positioning of the second conductive layer relative to the first layer. Rather than creating a perfectly symmetric mirrored structure, the second layer is positioned at a substantial offset distance below the first insulating substrate. This asymmetric arrangement, combined with the transpose configuration, maximizes the inductance reduction effect through opposite current directions while providing manufacturing tolerance for alignment variations.
Applied Scientific Principles
This section explains which scientific principles are used to turn an abstract innovation direction into a practical engineering solution.
Function Achieved in This Case
This solution significantly reduces the inductance of the current circulation loop from values greater than 30 nH to less than 10 nH, enabling faster switching of electronic components and minimizing overvoltages and oscillations.
Implementation Method 1
the second and third conductive layers forming a second current flow plane substantially parallel to the first flow plane, the second conductive layer being substantially the transpose of the first one conductive layer in a direction perpendicular to the first plane, and an electrical connection between the two circulation planes, so that the electric current is capable of circulating from the first terminal to the second terminal in the two parallel circulation planes via the electrical connection, the direction of circulation of the current in the second plane being opposite to that of the current in the first plane
Data Source
Figure 1
Figure 2
AI summary
The device (14) has a connection plate (51) including an electrically conductive layer (68) that is in contact with a lower planar surface (66) of the plate. The conductive layer forms an additional current flowing plane (P3) that is parallel to first and second current flowing planes (P1, P2) formed by other electrically conductive layers (36, 44), where flow direction (I3) of current in the additional plane is identical to flow direction (I1) of the current in the first plane. An electric connector (48) ensures connection between the first and second planes. The electric connector is formed of a copper plate.