Interconnection Element Structure for RDL Pad Crack Resistance
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Solution Overview
Problem
Existing electrical components face issues with cracking and fatigue in the redistribution layer pad due to thermal expansion differences, leading to potential open circuits or intermittent contacts, especially under temperature variations.
Innovation Solution
A layered electrical component configuration with a dielectric layer opening featuring protrusions to distribute mechanical stress and prevent crack propagation, maintaining electrical continuity without altering the component's dimensions or manufacturing process.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Reliability
If conventional wire bonding or flip chip methods are used, then electrical connections can be established, but the device footprint is large and interconnect reliability is compromised due to stress on solder joints
Solution Approach 1:
The patent transitions from planar wire bonding to three-dimensional vertical interconnections using through-substrate vias and stacked semiconductor dies. This dimensional change allows interconnects to pass through the substrate vertically rather than traveling laterally on the surface, significantly reducing the device footprint while maintaining connection reliability through direct vertical pathways.
Solution Approach 2:
The patent implements nested interconnect structures where through-substrate vias are embedded within the substrate, and additional vias are created within existing vias to achieve three-dimensional stacking. This nesting approach allows multiple interconnection levels to be integrated within a compact volume, reducing footprint while maintaining reliable electrical connections between stacked dies.
2Ease of operation
If solder joints are used for connecting semiconductor devices, then electrical connections are established, but the solder joints are vulnerable to stress from thermal expansion and handling
Solution Approach 1:
The patent introduces an intermediary approach by using through-substrate vias filled with conductive material as a robust mechanical and electrical intermediary between stacked semiconductor dies. This intermediary structure provides a stress-resistant connection that is less vulnerable to thermal expansion and handling stresses compared to traditional solder joints, while still establishing reliable electrical connections.
Solution Approach 2:
The patent employs composite interconnect structures combining multiple materials within through-substrate vias, including conductive fill materials, barrier layers, and adhesive layers. This composite approach creates a robust interconnection that resists thermal stress and mechanical handling while maintaining electrical conductivity, improving both handling robustness and reliability.
3Area of stationary object
If through-substrate vias are used to reduce device footprint, then footprint is reduced, but via alignment precision and filling reliability become more difficult to achieve
Solution Approach 1:
The patent applies preliminary action by forming via holes and applying adhesive layers or barrier coatings before inserting conductive fill materials into through-substrate vias. This preliminary preparation ensures proper via alignment and creates a reliable bonding interface, making the subsequent filling process more reliable and easier to control, thereby improving manufacturing precision.
Solution Approach 2:
The patent implements self-alignment mechanisms where the via structure itself provides alignment references for subsequent processing steps. The rigid substrate and precisely formed via holes serve as self-aligning features that guide the placement of stacked dies and conductive materials, reducing the need for external alignment systems and improving via alignment precision.
Data Source
Figure 1A~1B
Figure 2~3
Figure 4~5
AI summary
An electrical component including a substrate, a first dielectric layer on the substrate, a redistribution layer pad on the first dielectric layer, and a component interconnection element on the redistribution layer pad so that the component interconnection element fills an opening in the second dielectric layer. The opening includes at least one protrusion between the component interconnection element solder ball metallization and the redistribution layer pad.