Integrated Interdigital Capacitor Package for POL Noise Shunting
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Solution Overview
Problem
Point-of-load (POL) converters in space environments suffer from input and output noise due to energized particles, necessitating a solution that maintains a stable output voltage while minimizing volume, weight, and power efficiency, and adhering to limited form factor constraints.
Innovation Solution
A package design incorporating interdigital capacitors and surface-mount capacitors on a single substrate, with interdigital capacitors providing high-frequency shunt capacitance to filter noise without additional volume, and surface-mount capacitors enhancing capacitance values in parallel.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Object-affected harmful factors
If additional discrete capacitors are added to filter high-frequency noise, then noise filtering performance is improved, but device footprint and form factor increase
Solution Approach 1:
The patent combines multiple capacitor functions (input capacitance, output capacitance, and high-frequency shunt capacitance) into a single integrated substrate structure. The interdigital capacitor patterns are formed directly on the substrate, merging what would traditionally be separate discrete components into one unified device, thereby eliminating the need for additional footprint space while maintaining noise filtering performance
Solution Approach 2:
The patent transitions from using discrete three-dimensional capacitor components to planar interdigital capacitor patterns formed on the substrate surface. This dimensional change allows capacitance to be achieved within the two-dimensional plane of the substrate rather than requiring additional vertical stacking or external components, thus maintaining a compact form factor
2Stability of the object's composition
If larger capacitors are used to maintain voltage stability, then output voltage stability is improved, but device volume and weight increase
Solution Approach 1:
The patent integrates input capacitors, output capacitors, and shunt capacitors into a single substrate structure with multiple interdigital capacitor patterns. This merging allows the device to achieve superior voltage stability and noise filtering without requiring larger individual capacitor components or increasing overall device volume
Solution Approach 2:
The patent uses a composite structure combining the substrate material with conductive layers forming interdigital patterns, and optionally surface-mount capacitors. This composite approach enables high capacitance values and effective noise filtering within a compact volume by leveraging the properties of multiple materials working together
3Reliability
If multiple discrete components are used to achieve required capacitance values, then capacitance performance is improved, but manufacturing complexity increases
Solution Approach 1:
The patent combines multiple capacitor functions into a single integrated substrate structure with interdigital patterns, reducing the number of discrete components and interconnections required. This integration simplifies the manufacturing process by reducing assembly steps while maintaining the reliability benefits of multiple capacitance functions working together
Solution Approach 2:
The substrate structure serves multiple functions simultaneously: it provides mechanical support, electrical connections, and multiple capacitance functions (input, output, and shunt). This multi-functionality reduces the overall component count and simplifies manufacturing compared to using separate discrete components for each function
Applied Scientific Principles
This section explains which scientific principles are used to turn an abstract innovation direction into a practical engineering solution.
Function Achieved in This Case
The package achieves a stable output voltage variation of 1*10⁻⁶ percent or less by shunting high-frequency noise, maintaining voltage stability without increasing footprint or form factor.
Implementation Method 1
the first plurality of fingers is interdigitated with the second plurality of fingers to form a first interdigital capacitor
Implementation Method 2
providing high-frequency shunt capacitance to filter noise
Implementation Method 3
The first surface-mount capacitor is electrically coupled in parallel with the first interdigital capacitor between the output node and the ground plane
Data Source
AI summary
A package is described. The package includes a die covered by a lid. The lid maintains a hermetic seal for the die. The package includes high frequency shunt capacitance in parallel with surface-mount capacitors. The high frequency shunt capacitance is formed by interdigital capacitors below the surface-mount capacitors. The interdigital capacitors, the surface-mount capacitors, and the die form a circuit which produces a stable output voltage. The output voltage may remain stable even when subject to noise due to energized particles in space. The package includes solder resist with openings for attaching the surface-mount capacitors to the interdigital capacitors. Advantageously, the interdigital capacitors may achieve high frequency shunt capacitance on the order of nano-farads as part of the frame geometry with minimal increase in package height.