Interdigitated Multilayer Capacitors for High Density and Breakdown Voltage
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Solution Overview
Problem
Current capacitor designs face challenges in achieving high capacitance density and breakdown voltage without increasing complexity or cost, as existing approaches either compromise on capacitance density or breakdown voltage.
Innovation Solution
The design incorporates a multilayer structure with interdigitated fingers in metal-oxide-semiconductor capacitors, where multiple layers of conductive and insulating materials are used to increase capacitance density without adding additional masks or layers, and the capacitors are arranged to enhance breakdown voltage.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Quantity of substance
If traditional capacitor designs are used, then manufacturing process remains simple, but capacitance density is low
Solution Approach 1:
The patent transitions from planar capacitor plates to three-dimensional interdigitated finger structures. Multiple fingers extend in the lateral direction, creating overlapping conductive regions that increase capacitance density without requiring additional vertical layers or masks. This dimensional transformation allows capacitance to scale with lateral footprint rather than being constrained by planar area alone.
Solution Approach 2:
The capacitor electrodes are divided into multiple interdigitated fingers rather than using single continuous plates. This segmentation increases the effective overlapping area between conductive regions, thereby increasing capacitance density. The fingers can be arranged in various patterns to optimize the overlapping area within the available footprint.
2Volume of moving object
If capacitor size is reduced, then circuit size decreases, but breakdown voltage decreases
Solution Approach 1:
The patent modifies the geometric parameters of the capacitor structure by creating interdigitated fingers with specific overlapping areas and spacing. This changes the electric field distribution and increases the effective capacitance per unit area, allowing smaller physical dimensions while maintaining or improving breakdown voltage characteristics.
Solution Approach 2:
The patent employs multiple conductive layers and insulating materials in a composite structure. The interdigitated fingers utilize overlapping conductive regions separated by dielectric materials, creating a composite architecture that enhances both capacitance density and breakdown voltage within a compact footprint.
Applied Scientific Principles
This section explains which scientific principles are used to turn an abstract innovation direction into a practical engineering solution.
Function Achieved in This Case
This approach significantly increases capacitance density while maintaining or improving breakdown voltage, reducing the overall circuit size without increasing complexity or cost.
Implementation Method 1
a first capacitor that can have a semiconductor layer, an insulating layer over the semiconductor layer, and a conductive layer over the insulating layer
Implementation Method 2
The first plurality of fingers can extend fully across the area where the conductive layer overlaps the semiconductor layer
Data Source
AI summary
A circuit can include a capacitor that has a semiconductor layer, a dielectric layer, and a conductive layer. The circuit can include an insulating layer and a metal or conductive layer. The metal layer can have a first portion that has a first plurality of fingers, and a second portion that has a second plurality of fingers, which can be interdigitated with the first plurality of fingers. The circuit can include one or more first electrical connections that electrically couple the first portion of the metal layer to the semiconductor layer of the capacitor. The circuit can include one or more second electrical connections that electrically couple the second portion of the metal layer to the conductive layer of the capacitor. A capacitance provided by the interdigitated first and second pluralities of fingers can be at least about 3% of a capacitance provided by the capacitor.