Interdigitated High-Voltage Isolation for 3D NAND Memory Arrays
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Solution Overview
Problem
Current semiconductor memory devices face challenges in efficiently isolating high voltage operations from low voltage components, leading to increased manufacturing costs and potential leakage currents due to the large footprint of isolation devices in 3D NAND memory devices.
Innovation Solution
The implementation of narrow active areas with interdigitated gate structures and a common gate configuration allows for efficient coupling and decoupling of memory cells to page buffers, reducing the area occupied by isolation devices while minimizing leakage currents by distributing high voltages across LDD regions.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Reliability
If traditional isolation devices are used to isolate high voltage operations from low voltage components, then high voltage isolation is achieved, but the footprint area increases and manufacturing costs increase
Solution Approach 1:
The isolation device is segmented into multiple narrow active areas (first through fourth active areas) arranged in a compact configuration. Each active area handles specific voltage isolation tasks, allowing the overall isolation function to be distributed across a smaller footprint area while maintaining effective high voltage isolation from low voltage components.
Solution Approach 2:
Multiple isolation functions are merged into a single integrated isolation device structure. The first and second active areas isolate high voltage from low voltage components, while the third and fourth active areas provide additional isolation pathways, combining these functions in a compact arrangement that reduces total footprint compared to separate isolation devices.
2Area of stationary object
If isolation device footprint is reduced to increase memory cell density, then area efficiency improves, but leakage currents may increase
Solution Approach 1:
The isolation device is divided into multiple narrow active areas that distribute the isolation function across several small regions. This segmentation allows for better control of leakage currents in each individual active area while maintaining compact overall dimensions, as each narrow active area can be optimized to minimize leakage paths.
Solution Approach 2:
Each active area is designed with specific local characteristics optimized for its isolation function. The narrow width of each active area (e.g., 50-150 nm) is specifically tailored to provide adequate isolation while minimizing leakage, and the arrangement of these areas with respect to bit lines and page buffers is optimized locally to reduce leakage currents in critical regions.
3Area of stationary object
If narrow active areas with interdigitated gate structures are used, then area occupied by isolation devices is reduced, but device complexity increases
Solution Approach 1:
The gate structure is segmented into multiple gates (first gate, second gate, third gate, fourth gate) that are interdigitated with corresponding narrow active areas. This segmentation allows for independent control of each active area while maintaining a compact interdigitated layout, reducing the overall footprint despite the increased number of gate components.
Solution Approach 2:
The interdigitated arrangement of gates and active areas utilizes a two-dimensional layout optimization where gates and active areas are arranged in alternating fingers. This dimensional arrangement maximizes the use of available space, allowing multiple isolation functions to be packed into a smaller footprint area while the complexity is managed through systematic patterning rather than three-dimensional stacking.
Applied Scientific Principles
This section explains which scientific principles are used to turn an abstract innovation direction into a practical engineering solution.
Function Achieved in This Case
This configuration effectively reduces the footprint of isolation devices, supports high voltage operations while minimizing leakage currents, and enhances the density of memory cells per unit area, thereby reducing manufacturing costs and improving operational reliability.
Implementation Method 1
a gate dielectric material between the gate and the active area
Implementation Method 2
gates coupled with the narrow active areas to control conductivities of the narrow active areas
Data Source
AI summary
High voltage isolation devices for semiconductor devices and associated systems, are disclosed herein. The isolation device may support operations of a 3-dimensional NAND memory array of the semiconductor device. In some embodiments, during high voltage operations (e.g., erase operations), the isolation device may provide a high voltage to the memory array while isolating other circuitry supporting low voltage operations of the memory array from the high voltage. The isolation device may include a set of narrow active areas separating the low voltage circuitry from the high voltage and a gate over the narrow active areas. In a further embodiment, the isolation device includes interdigitated narrow active areas and a common gate over the interdigitated narrow active areas to reduce an area occupied by the isolation devices.