Interface Circuit for Clock Domain Data Transfer
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Solution Overview
Problem
Transferring data between different clock domains is challenging due to the lack of a common clock, leading to metastability issues and the need for slow handshake protocols or expensive dual-port RAM.
Innovation Solution
An interface circuit portion with a shared memory and signaling mechanisms that use a data valid signal to change the state of an interface signal, allowing data to be transferred reliably between clock domains without the need for lengthy handshake procedures or large dual-port RAM.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Reliability
If handshake protocols are used for data transfer between clock domains, then reliability is improved, but transfer speed deteriorates
Solution Approach 1:
The patent extracts the essential signaling function from the complex two-way handshake protocol, retaining only the necessary one-way interface signal that indicates data presence. This simplifies the protocol while maintaining reliability, eliminating the need for lengthy acknowledge sequences and improving transfer speed.
Solution Approach 2:
The interface signal is generated in advance to indicate when data is present in the shared memory, allowing the receiving circuit to prepare for data capture without waiting for complex handshake sequences. This preliminary indication maintains reliability while significantly reducing transfer latency.
2Reliability
If dual port RAM is used for data transfer between clock domains, then transfer reliability is improved, but device cost and physical space increase
Solution Approach 1:
The patent segments the data transfer function into three separate portions: data storage portion, signaling portion, and data access portion. This segmentation allows each portion to be optimized independently and reduces the need for large dual-port RAM structures, lowering device cost and physical space requirements while maintaining transfer reliability.
Solution Approach 2:
The shared memory structure serves multiple functions: it stores data, generates interface signals, and enables clock domain crossing. This multi-functionality replaces the need for dedicated dual-port RAM, reducing overall device complexity and cost while maintaining reliable data transfer between different clock domains.
3Ease of operation
If synchronous sampling is used in clock domain crossing, then data validity detection is simplified, but clock frequency matching requirements increase system complexity
Solution Approach 1:
The interface signal acts as an intermediary between the first and second clock domains, carrying data presence information without requiring direct clock synchronization. This mediator enables the receiving circuit to sample data at its own clock frequency while maintaining data validity detection, simplifying operation without requiring complex clock frequency matching.
Data Source
AI summary
A system comprises a first circuit portion operating with a first clock having a first frequency, a second circuit portion operating with a second clock having a second, higher frequency, and an interface circuit portion for transferring data from the first and the second circuit portions. The first circuit portion is arranged to assert a data valid signal when asserting data at a data input. The data storage portion is configured to detect the data valid signal and to change an input data storage location of a shared memory in response thereto. The signalling portion is configured to change a state of an interface signal in response to the data valid signal. The data access portion is configured to change an output data storage location in response to the change of state of an interface signal and to output a data ready signal to the second circuit portion.