Cross-Power-Domain Interface Circuit for ESD-Resistant Logic Transfer
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Solution Overview
Problem
The transmission of logical signal levels between power domain circuits in a chip is prone to errors due to electrostatic interference, which causes fluctuations in the turnover voltage, leading to incorrect interpretation of signal levels.
Innovation Solution
An interface circuit with a phase inverter is introduced, where the phase inverter transitions between logical states of a signal. It is configured such that when a signal from one power domain circuit is input, the output is correctly aligned with the logical levels of the receiving power domain circuit, even under conditions of electrostatic interference.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Reliability
If an ESD device (such as TVS diode or series resistor) is added outside the chip to discharge static electricity, then the electrostatic discharge capability is improved, but the packaging cost and chip area increase
Solution Approach 1:
The patent extracts the electrostatic discharge function from external ESD devices and relocates it inside the chip by utilizing the intrinsic body diode of the output transistor. This eliminates the need for external ESD protection components, thereby reducing packaging cost and chip area while maintaining electrostatic discharge capability
Solution Approach 2:
The output transistor's body diode is utilized to provide electrostatic discharge protection without requiring additional dedicated ESD protection components. The transistor itself serves the dual function of signal output and electrostatic protection, achieving self-service and reducing overall device complexity
2Reliability
If the quantity of output pins of the ground cable in the chip is increased to enhance electrostatic discharge capability, then the electrostatic discharge capability is improved, but the chip area and packaging cost increase
Solution Approach 1:
The output pin is designed to serve multiple functions: normal signal output and electrostatic discharge. By configuring the output transistor's body diode to conduct during electrostatic events, the same pin structure handles both signal transmission and protection, eliminating the need for separate protection pins and reducing overall chip area
3Reliability
If the turnover voltage of a power domain circuit changes due to electrostatic interference, then the signal transmission accuracy deteriorates, but adding ESD protection increases device complexity
Solution Approach 1:
The output transistor's body diode provides preemptive protection against voltage fluctuations caused by electrostatic interference. By being inherently present in the transistor structure, it cushions against voltage changes before they can cause signal transmission errors, maintaining accuracy without adding complex protection circuits
Data Source
Figure 1A
Figure 1B
Figure 1C~2A
AI summary
This application discloses an interface circuit, and relates to the field of electronic technologies. The interface circuit includes a phase inverter. An input end of the phase inverter is connected to a signal output end of a first power domain circuit, and an output end of the phase inverter is connected to a signal input end of a second power domain circuit. A power end of the phase inverter is connected to a power supply of the first power domain circuit, and a ground end of the phase inverter is connected to a reference ground of the second power domain circuit. Alternatively, a power end of the phase inverter is connected to a power supply of the second power domain circuit, and a ground end of the phase inverter is connected to a reference ground of the first power domain circuit. When a voltage of the power end of the phase inverter of the interface circuit is greater than a voltage of the ground end of the phase inverter, correct transmission of a logical level of a signal can be ensured, thereby ensuring stability and reliability of a data transmission link between the first power domain circuit and the second power domain circuit, and enhancing an electrostatic interference resistance capability of a chip disposed with the interface circuit.