Communication Interface Device Terminal Segmentation
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Solution Overview
Problem
Existing communication interface methods, such as those using SPI and I2C protocols, face issues with erroneous operations and complex control when multiple LSIs with different protocol requirements are connected to an interface bus, leading to compromised communication quality and increased chip size due to shared terminals for clock and data signals.
Innovation Solution
A communication interface device configuration that separates the terminals for clock and data signals between SPI and I2C interface circuits, using a D flip-flop and selector to ensure exclusive operation of one interface protocol without sharing terminals, and optionally includes a noise filter and detection controlling unit to prevent erroneous operations and simplify control.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Device complexity
If terminals for clock and data signals are shared between SPI and I2C interface circuits, then device complexity is reduced, but erroneous operations occur due to protocol conflicts
Solution Approach 1:
The patent segments the terminal functions by separating clock and data signal terminals between SPI and I2C interface circuits. Specifically, the SPI interface uses separate clock terminal (pin 2) and data terminal (pin 3), while the I2C interface uses different clock terminal (pin 1) and data terminal (pin 4). This segmentation prevents protocol conflicts by ensuring that when one interface is active, the other interface's terminals are not simultaneously accessed, thereby eliminating erroneous operations while maintaining a relatively simple device structure.
2Reliability
If additional terminals are added for protocol selection, then communication reliability is improved, but chip size increases
Solution Approach 1:
The patent implements multi-functionality by designing each terminal to serve dual purposes depending on the active interface protocol. The clock terminals (pins 1 and 2) and data terminals (pins 3 and 4) can be used by either SPI or I2C interfaces based on which protocol is currently active. This universal design allows the interface device to recognize and switch between protocols without requiring additional dedicated terminals for protocol selection, thereby improving communication reliability while avoiding chip size increase.
3Reliability
If separate terminals are used for SPI and I2C interfaces, then communication quality is improved, but device complexity increases
Solution Approach 1:
The patent employs asymmetric terminal configuration where SPI interface uses pins 2 and 3 for clock and data respectively, while I2C interface uses pins 1 and 4 for clock and data respectively. This asymmetric design provides clear physical separation between the two interface protocols, ensuring that clock and data signals are transmitted through dedicated terminals for each protocol. The asymmetry prevents signal interference and protocol conflicts, thereby improving communication quality while maintaining manageable device complexity through systematic pin assignment.
Data Source
AI summary
A communication interface device includes: a first interface circuit including a chip select terminal connected to a first terminal, a clock terminal connected to a second terminal, and a data terminal connected to a third terminal; and a second interface circuit including a second clock terminal connected to the first terminal and a data terminal connected to the third terminal. In a case of performing communication by the first interface circuit, a fixed signal fixed at a predetermined level is input into the first terminal, a clock signal is input into the second terminal, and a data signal is input into the third terminal, and in a case of performing communication by the second interface circuit, the clock signal is input into the first terminal and the data signal is input into the third terminal.