Interior Leadframe Packaging for Higher I/O Density
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Solution Overview
Problem
Existing electronic device packaging solutions struggle to increase input/output (I/O) density without increasing package dimensions or requiring additional fabrication processing and higher costs, as seen in flip-chip on lead (FCOL) and grid array packages.
Innovation Solution
The integration of both peripheral and interior leads with specific package structures, where interior leads are positioned under the package, allowing for increased I/O density without increasing device size, and using a lead frame fabrication method that includes recess formation and molding processes to create these structures.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Quantity of substance
If functional leads are placed only on the edges of the package (conventional QFN packaging), then the package structure is simple and manufacturing is easier, but the I/O density cannot be increased without increasing the overall package dimensions
Solution Approach 1:
The patent transitions from a two-dimensional edge-only lead arrangement to a three-dimensional configuration by placing leads on the peripheral edges and additional functional leads in the interior region underneath the package body. This dimensional change allows I/O connections to be made from both the side and bottom of the package, effectively doubling the I/O density without increasing the package footprint.
Solution Approach 2:
The lead structure is segmented into two distinct groups: peripheral leads located on the outer edges of the package and interior leads positioned in the interior region underneath the package body. This segmentation allows each group of leads to serve independent functions, with peripheral leads providing structural support and edge connections while interior leads provide additional I/O connections, thereby increasing overall I/O density.
2Quantity of substance
If grid array packages (LGA, BGA) are used to increase I/O density, then more I/O connections are achieved, but additional fabrication processing is required and product cost increases
Solution Approach 1:
The patent combines the advantages of conventional QFN packaging with grid array packaging by integrating both peripheral leads and interior leads into a single package structure. This merging allows the device to achieve high I/O density comparable to grid array packages while maintaining the simpler manufacturing process and lower cost associated with conventional QFN packaging, as the lead frame structure can be formed using standard fabrication techniques.
3Temperature
If FCOL small outline transistor packages are used, then thermal performance is improved, but I/O density cannot be increased without increasing package size
Solution Approach 1:
The interior leads positioned underneath the package body serve multiple functions: they provide additional I/O connections for increased I/O density, acts as heat sinks to improve thermal performance by conducting heat away from the semiconductor die, and contribute to the structural integrity of the package. This multi-functionality allows the package to achieve both high I/O density and improved thermal management without increasing package dimensions.
Data Source
AI summary
An electronic device includes peripheral first leads, interior second leads, a first package structure extending on top sides of the peripheral first leads and interior second leads, and on upper first portions of lateral sides of the interior second leads, and a second package structure extending laterally around lower second portions of the lateral sides of the interior second leads, the second package structure exposing the bottom side of each of the peripheral first leads and exposing one lateral side of each of the peripheral first leads, the second package structure exposing the bottom side of each of the interior second leads.