3D Memory Die Layout With Interlaced Contact Regions and Vertical Vias
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Solution Overview
Problem
Current three-dimensional memory devices face challenges in efficiently integrating separated contact regions that are laterally spaced apart, which affects the performance and scalability of memory arrays.
Innovation Solution
A semiconductor structure and method for forming a memory die with alternating stacks of insulating and electrically conductive layers over a substrate, featuring distinct contact and memory array regions, where electrically conductive layers extend continuously through these regions, and contact via structures connect the layers for logic die bonding.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Ease of manufacture
If separated contact regions are laterally spaced apart in three-dimensional memory devices, then integration of contact regions is improved, but electrical connectivity between contact and memory regions deteriorates
Solution Approach 1:
The patent transitions from lateral connectivity to vertical connectivity by extending electrically conductive layers through the alternating stack in the vertical dimension. Contact via structures are formed to penetrate through insulating and conductive layers, establishing vertical electrical pathways that connect laterally separated contact regions to memory regions below, thus resolving the connectivity issue while maintaining lateral separation.
Solution Approach 2:
The patent introduces electrically conductive layers as intermediary elements that bridge the gap between laterally separated contact regions and memory regions. These conductive layers extend continuously through the alternating stack and are connected via contact via structures, serving as mediators that maintain electrical connectivity despite lateral spacing between contact regions.
2Reliability
If electrically conductive layers extend continuously through contact and memory array regions, then electrical connectivity is improved, but device complexity increases
Solution Approach 1:
The electrically conductive layers serve multiple functions simultaneously: they act as continuous conductive pathways for electrical connectivity, serve as structural frameworks for the alternating stack, and provide bonding surfaces for contact via structures. This multi-functionality reduces the need for separate dedicated structures, thereby managing complexity while achieving reliable connectivity.
Solution Approach 2:
The patent merges the functions of separate conductive pathways into a single continuous electrically conductive layer that extends through both contact and memory array regions. This consolidation reduces the number of discrete components and simplifies the overall structure compared to having separate conductive elements for each region.
3Manufacturing precision
If contact via structures are formed to contact specific electrically conductive layers, then manufacturing precision is improved, but process complexity increases
Solution Approach 1:
The patent segments the formation of contact via structures into distinct stages, with each via structure formed to contact a specific electrically conductive layer at a predetermined location. This segmentation allows for precise control over which layers are connected, enabling manufacturing precision while organizing the complex process into manageable, sequential steps.
Solution Approach 2:
The patent employs preliminary patterning and positioning of contact via structures before final assembly and bonding. Contact via structures are pre-formed to contact specific electrically conductive layers at designated locations, allowing for precise alignment and connection establishment before the memory die is bonded to the logic die, thereby managing process complexity through advance preparation.
Data Source
AI summary
A memory die includes an alternating stack of insulating layers and electrically conductive layers through which memory opening fill structures vertically extend. The memory die includes at least three memory array regions interlaced with at least two contact regions, or at least three contact regions interlaced with at least two memory array regions in the same memory plane. A logic die including at least two word line driver regions can be bonded to the memory die. The interlacing of the contact regions and the memory array regions can reduce lateral offset of boundaries of the word line driver regions from boundaries of the contact regions.