Single-Layer Interlayer Dielectric with Porosity Gradient
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Solution Overview
Problem
Conventional semiconductor devices with low-dielectric-constant interlayer dielectrics face issues of increased interconnect capacitance, leading to decreased operation speed and reliability due to film separation and leakage paths at interfaces between different film layers.
Innovation Solution
A semiconductor device with a single-layer interlayer dielectric structure having varying porosity in the thickness direction, eliminating film interfaces and leveraging porosity profiles to enhance etch selectivity and reduce leakage, formed using a precursor and pore-forming materials through chemical vapor deposition.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Manufacturing precision
If a multi-layer interlayer dielectric structure with different carbon contents is used to increase etch selectivity, then the etch selectivity to the via layer insulating film is improved and the depth of the interconnect trench becomes uniform, but the interface between different films separates and forms leakage paths between adjacent interconnects or vias, degrading device reliability
Solution Approach 1:
The patent merges the via layer insulating film and interconnect layer insulating film into a single continuous low-dielectric-constant interlayer dielectric layer, eliminating the interface between different films while maintaining etch selectivity through controlled porosity gradients and composition variations within the unified structure
Solution Approach 2:
The patent applies local quality by creating regions with different porosity and carbon content within the single interlayer dielectric layer - the via region has lower porosity and higher carbon content for etch resistance, while the interconnect region has higher porosity and lower carbon content for low capacitance, achieving both etch selectivity and reliability without interfaces
2Manufacturing precision
If the carbon content of the interconnect layer insulating film is increased to improve etch selectivity, then the etch rate increases and etch selectivity is improved, but the dielectric constant increases leading to higher interconnect capacitance and decreased operation speed
Solution Approach 1:
The patent applies local quality by creating spatially varying composition and porosity within the single interlayer dielectric layer - the via region has higher carbon content for etch resistance while the interconnect region has lower carbon content and higher porosity for low dielectric constant, achieving both etch selectivity and high-speed operation without compromise
Applied Scientific Principles
This section explains which scientific principles are used to turn an abstract innovation direction into a practical engineering solution.
Function Achieved in This Case
The solution increases the reliability of semiconductor devices by preventing film separation and leakage, while providing greater control over interconnect resistance and capacitance through controlled porosity profiles, thereby improving fabrication consistency.
Implementation Method 1
suppress the increase in interconnect capacitance by using a material having a low dielectric constant for an interlayer dielectric
Implementation Method 2
development and practical use of a material of which the dielectric constant is reduced by making SiOC, etc., porous
Implementation Method 3
formed using a precursor and pore-forming materials through chemical vapor deposition
Data Source
AI summary
A semiconductor device includes an interlayer dielectric with a single-layer structure having a plurality of pores. The porosity of the interlayer dielectric per unit volume varies in a thickness direction.