Interleaved Backpropagation Neural Network Processor
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Solution Overview
Problem
Current hardware solutions for deep neural networks (DNNs) face limitations in scalability and efficiency due to capacity constraints, particularly in applications like vehicle classification, where high memory access and computation time are required, leading to increased latency and power consumption.
Innovation Solution
The implementation of a processing circuitry that interleaves forward propagation of input values and backward propagation of error values in a field programmable gate array (FPGA), utilizing a system-on-chip (SoC) with on-chip static random access memory (SRAM) and external dynamic random access memory (DRAM), allowing for co-occurrence of these processes to optimize memory usage and reduce power consumption.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Loss of time
If forward propagation and backward propagation are performed sequentially using external DRAM, then memory capacity is sufficient, but computation time and energy consumption increase
Solution Approach 1:
The patent divides the memory system into two segments: on-chip SRAM for frequently accessed weight values and external DRAM for bulk storage. This segmentation allows the system to keep critical data in fast, energy-efficient on-chip memory while maintaining sufficient total capacity through external memory, thereby reducing both computation time and energy consumption for memory access operations.
Solution Approach 2:
The patent implements preliminary action by loading weight values from external DRAM into on-chip SRAM before they are needed for computation. This pre-loading strategy ensures that weight values are already in fast on-chip memory when forward and backward propagation operations require them, eliminating the need for energy-consuming and time-consuming external memory access during critical computation phases.
2Speed
If weight values are stored in external DRAM, then memory capacity is sufficient, but access latency increases
Solution Approach 1:
The patent adds a spatial dimension to the memory hierarchy by implementing an on-chip SRAM layer between the processor and external DRAM. This creates a multi-level memory architecture where frequently accessed weight values reside in the on-chip SRAM layer, providing fast access speeds, while the external DRAM layer provides bulk storage capacity. This dimensional addition to the memory system resolves the contradiction between access speed and capacity.
Data Source
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AI summary
Processing circuitry for a deep neural network can include input/output ports, and a plurality of neural network layers coupled in order from a first layer to a last layer, each of the plurality of neural network layers including a plurality of weighted computational units having circuitry to interleave forward propagation of computational unit input values from the first layer to the last layer and backward propagation of output error values from the last layer to the first layer.