Interleaved FEC Codewords for Low-Latency High-Speed Serial Links
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Solution Overview
Problem
As data rates in serial interconnects such as PCIe increase, maintaining bit error rates (BER) of 10−12 across hundreds of lanes per System on Chip (SoC) becomes challenging due to factors like cross-talk, inter-symbol interference, and channel loss, leading to latency and bandwidth loss issues with conventional Forward Error Correction (FEC) methods.
Innovation Solution
Implementing a single-symbol correct FEC with interleaved error correcting code words and dynamic switching of code sizes to mitigate latency and bandwidth loss, using a parity-check matrix for efficient error correction across lanes, and adapting FEC length based on bandwidth utilization.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Reliability
If conventional FEC methods are used to maintain bit error rates at 10^-12 in high-speed serial interconnects, then error correction reliability is improved, but latency and bandwidth loss increase
Solution Approach 1:
The patent segments the FEC code words into multiple smaller code words that are interleaved across different lanes. Instead of using a single large FEC code word that processes all data sequentially (causing high latency), the system divides the correction workload into parallel segments that can be processed simultaneously across multiple lanes, reducing latency while maintaining error correction reliability.
Solution Approach 2:
The patent introduces the dimension of lane parallelism to FEC processing. By distributing FEC code words across multiple lanes rather than processing them sequentially in a single lane, the system achieves parallel error correction operations. This dimensional shift from sequential to parallel processing reduces the latency penalty associated with conventional FEC methods.
2Reliability
If FEC code words are added to correct errors in high-speed serial interconnects, then error correction capability is improved, but bandwidth efficiency deteriorates
Solution Approach 1:
The patent segments the FEC overhead by distributing code words across multiple lanes rather than concentrating all FEC bits in a single lane. This segmentation allows the system to maintain error correction capability while reducing the impact on bandwidth efficiency, as the overhead is spread out and processed in parallel across multiple channels.
Solution Approach 2:
The patent implements dynamic switching between different FEC code sizes based on link conditions and bandwidth demands. The system can adapt the FEC configuration dynamically, selecting appropriate code lengths and distributions to optimize the balance between error correction capability and bandwidth efficiency for different operating conditions.
Data Source
AI summary
Systems and devices can include a port for transmitting data; and a link coupled to the port. The port, in preparation to transmit a data block across the link, to determine a size of a burst of data to be transmitted across the link; determine a plurality of error correcting code words for forward error correction based on the size of the burst of data; interleave each of the plurality of error correcting code words to correspond with consecutive symbols of the burst of data; and transmit the burst of data comprising the interleaved plurality of error correcting code across the link.