Forward Error Control Use TRIZ Cases
- List Decoding Parity Check Before CRC to Cut Latency
Parity checks prune invalid list-decoding candidates before CRC, reducing latency, power, memory use, and output lists.
- Ethernet Auto-Negotiation Bits for Higher FEC Signaling Capacity
Single-bit FEC signaling expands Ethernet basic-page capacity, reducing extra negotiation pages and preserving auto-negotiation speed.
- PMA Interleaving in Ethernet PHY for High-Rate BER Reduction
Adding symbol or convolutional interleaving in the PMA layer cuts BER in high-rate Ethernet without redesigning the PCS.
- Optical Transmission Modulation Switching for Short Data Frames
Adaptive multilevel modulation matches code format to short data blocks, reducing padding overhead while protecting control information.
- Segment-Interleaved Data Transmission for URAT Signal Separation
Segmenting, padding, and interleaving coded bits helps URAT terminals separate shared-resource signals for accurate base-station detection.
- Optical Transmission Coding With Adaptive Multilevel Modulation
Adaptive multilevel modulation and inserted control information let optical links match code format to data length and avoid fixed-value padding.
- Multi-Channel ECC Interleaving for Channel Failure Recovery
Interleaving ECC blocks across multiple channels preserves message recovery when high-BER or failed links disrupt data transmission.
- MAC Frame Check Sequence Verification for Corrupted Packet Detection
Precomputed FCS checking in the MAC layer catches memory-corrupted packets before transmission, reducing wasted retransmissions.