PMA Interleaving in Ethernet PHY for High-Rate BER Reduction

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Solution Overview

Problem

Existing methods for reducing bit error rate (BER) in Ethernet data transmission, such as forward error correction and interleaving by the physical coding sublayer (PCS), fail to meet the requirements when data transmission rates increase.

Innovation Solution

The PMA sublayer in the Ethernet device performs symbol or convolutional interleaving on the data stream, allowing for flexible interleaving designs without modifying the existing PCS, thereby reducing BER in high-rate scenarios.

Engineering Contradictions & Design Principles

VSEngineering Contradiction Analysis

1Reliability

If forward error correction and interleaving by PCS are used to reduce BER, then BER is reduced, but the method cannot meet requirements when data transmission rate increases

Engineering Contradiction:

Improvebit error rateVSAvoiddata transmission rate

Core Design Contradiction:

ReliabilityVSSpeed

Solution Approach 1:

The patent segments the interleaving function into two parts: the existing PCS interleaving and a new PMA sublayer interleaving. By dividing the error correction task across multiple layers (PCS and PMA), the system can handle higher transmission rates while maintaining BER performance, as each layer contributes to the overall error correction capability

Inventive Principle:

Principle #1Segmentation

Solution Approach 2:

The patent introduces the PMA sublayer as an intermediary between the PCS and the physical medium. This intermediary layer performs additional interleaving specifically designed for high-rate scenarios, bridging the gap between existing PCS capabilities and the requirements of high-speed transmission without modifying the original PCS structure

Inventive Principle:

Principle #24Intermediary (Mediator)

2Reliability

If PCS interleaving is used to reduce BER, then BER is reduced, but device complexity increases due to modification requirements

Engineering Contradiction:

Improvebit error rateVSAvoidPCS modification complexity

Core Design Contradiction:

ReliabilityVSDevice complexity

Solution Approach 1:

The patent separates the error correction functionality into distinct segments: the original PCS interleaving remains unchanged, while a new PMA sublayer is added to provide additional interleaving. This segmentation allows the system to achieve improved BER performance without complicating the existing PCS design

Inventive Principle:

Principle #1Segmentation

Solution Approach 2:

The patent extracts the high-rate interleaving requirement from the PCS and places it in the PMA sublayer. By taking out this specific function and locating it in a different layer, the PCS remains simple and unchanged, while the PMA sublayer handles the complex high-rate interleaving needs

Inventive Principle:

Principle #2Taking out (Extraction)

Data Source

PatentUS20250365094A1Data sending method, device, and system in ethernet

Publication Date: 2025.11.27 HUAWEI TECH CO LTD

AI summary

A data sending method, a device, and a system are provided. A physical medium attachment (PMA) sublayer of an Ethernet device obtains a forward error correction (FEC) encoded data stream, and performs a first data processing on the data stream, to obtain an interleaved data stream, where the first data processing includes performing interleaving in a first interleaving manner, and an interleaving type of the first interleaving manner is symbol interleaving or convolutional interleaving. According to this application, functions of the PMA sublayer can be extended, to meet a requirement for reducing a bit error rate (BER) in a high-rate Ethernet data transmission scenario.