Interleaved Majority Vote Circuit for Single-Cycle High-Speed Logic
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Solution Overview
Problem
Conventional majority vote circuits face challenges with speed, reliability, and size, particularly in high-speed applications where they are slow, inaccurate, and power-intensive, especially when dealing with large numbers of inputs.
Innovation Solution
The implementation of a majority voting circuit that interleaves data words between two out-of-phase majority vote blocks using a divided clock signal with half the frequency of the original clock, allowing for longer precharging and evaluation times, and independent of duty cycle variations, utilizing comparators and edge detectors to determine the majority logic state.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Speed
If conventional digital majority vote circuits are used, then the circuit can determine majority logic state, but the circuit is slow and cannot generate output in a single clock cycle
Solution Approach 1:
The patent divides the majority vote circuit into multiple parallel sub-circuits, each handling a portion of the input bits. This segmentation allows simultaneous processing of multiple bits, significantly increasing speed while maintaining accuracy through parallel evaluation paths.
Solution Approach 2:
The patent employs periodic precharging and evaluation phases in a clocked architecture. During precharge phases, capacitors are charged to known states, and during evaluation phases, the actual majority vote is performed. This periodic action enables single-clock-cycle operation while ensuring reliable results through controlled timing.
2Speed
If conventional analog majority vote circuits are used, then the circuit operates relatively fast, but it is not accurate or reliable especially for large numbers of inputs and consumes significant power
Solution Approach 1:
The patent replaces the continuous analog voltage comparison mechanism with discrete digital logic elements and capacitive storage. Instead of relying on analog voltage levels that are sensitive to noise and drift, the invention uses digital signals combined with precharged capacitors that provide stable, noise-immune operation for reliable majority determination.
Solution Approach 2:
The patent implements precharging of capacitors before the actual majority vote evaluation. This preliminary action sets known initial states for all storage elements, eliminating the need for complex analog threshold comparisons and ensuring reliable operation independent of input signal characteristics or noise conditions.
3Productivity
If conventional majority vote circuits are used, then the circuit can process data, but the circuit size is large
Solution Approach 1:
The patent merges multiple functions into shared circuit elements. The same capacitor arrays and logic gates are reused across different evaluation phases and data words through time-multiplexed operation. This merging significantly reduces the total component count and circuit area while maintaining full data processing capability.
Solution Approach 2:
The patent designs universal circuit blocks that can handle multiple input bits and operate across different clock cycles. The capacitive storage elements and logic gates serve multiple purposes: storing intermediate results, performing vote evaluation, and preparing for the next data word. This multi-functionality reduces overall circuit size while preserving productivity.
Data Source
AI summary
Data words from a parallel communication channel are interleaved to two majority vote blocks that operate out of phase, using a divided clock signal that has half the clock frequency of the clock signal associated with the parallel communication channel. As one majority vote block evaluates a data word and outputs a result, the other majority vote block is in pre-charge mode awaiting the next data for evaluation.