Interleaved Scan Architecture for Concurrent IC Testing
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Solution Overview
Problem
Conventional testing techniques for integrated circuits (ICs) face challenges in reducing test time and silicon complexity due to increased chip complexity, leading to higher costs and power consumption, particularly in methods that increase scan clock frequency or use double data rate (DDR) clocking.
Innovation Solution
An interleaved scan architecture that distributes test inputs and outputs across multiple IP blocks on independent power rails, using a lower second clock rate to relax timing constraints and avoid costly timing buffers, allowing concurrent testing.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Productivity
If scan clock frequency is increased to reduce test time, then test speed improves, but timing constraints become more difficult to meet and costly timing buffers are required
Solution Approach 1:
The chip is divided into multiple IP blocks, each with its own independent power rail. Test inputs are segmented and distributed to different IP blocks through the interleaved scan architecture, allowing concurrent testing without requiring centralized high-speed timing buffers.
Solution Approach 2:
The patent transitions from sequential testing along a single scan chain to concurrent testing across multiple dimensions by utilizing independent power rails as additional test dimensions. This allows simultaneous application of test vectors to multiple IP blocks without increasing clock frequency.
2Reliability
If conventional testing techniques are used for complex chips, then testing coverage is maintained, but test time increases leading to higher costs
Solution Approach 1:
The interleaved scan architecture enables continuous concurrent testing across multiple IP blocks simultaneously. While conventional methods test blocks sequentially, this architecture maintains useful testing action across all selected IP blocks at the same time, reducing total test time while preserving coverage.
Solution Approach 2:
The patent changes the testing parameter from sequential clock cycles to parallel clock cycles by utilizing independent power rails. Each IP block on a different power rail can be tested simultaneously with the same test clock, fundamentally changing the testing paradigm from serial to parallel operation.
3Manufacturing precision
If test-specific timing circuitry is added to meet timing constraints, then timing accuracy improves, but silicon complexity and cost increase
Solution Approach 1:
The patent extracts and removes the need for test-specific timing buffers and circuitry by using the existing independent power rail infrastructure for its intended purpose. The solution takes out the additional complexity by relying on already-present power distribution structures rather than adding dedicated timing control hardware.
4Productivity
If DDR clocking is used to increase test data rate, then test throughput improves, but power consumption increases
Solution Approach 1:
The patent uses periodic single-data-rate clocking applied periodically to each IP block on different power rails, achieving concurrent testing throughput without the continuous high-power demand of DDR clocking. Each power rail is activated periodically for its assigned IP blocks, reducing overall power consumption compared to sustained DDR operation.
Data Source
AI summary
This document describes apparatuses and techniques for an interleaved scan architecture for concurrent testing of integrated circuit (IC) chips. In various aspects, an IC or system-on-chip may include interleaved scan circuitry, IP blocks or functional blocks on independent power rails, block selection logic, and a scan out combiner. The interleaved scan circuitry can receive test signaling that includes a set of test input/outputs (I/Os) at a first clock rate and generate, based on the received test signaling, multiple sets of test I/Os at a second clock rate for distribution to respective ones of the blocks. In some aspects, the second clock rate is lower than the first clock rate, which enables relaxing of timing constraints during testing and avoids usage of costly test-specific timing buffers. As such, the described aspects can reduce chip test time and reduce silicon complexity by avoiding the need for test-specific timing or power circuitry.