Interleaved SOC Pad Layout for DDR Routing Congestion
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Solution Overview
Problem
The existing methods for reducing design costs in System on Chip (SOC) architectures, particularly for packaging, face challenges with the physical interface layout of large pin count parallel interfaces like the DDR interface, leading to routing congestion and wire sweep issues when repackaging from a 64-bit to a 32-bit interface.
Innovation Solution
The solution involves interleaving interface pads from different byte lanes to create a more even distribution of bond wires, allowing for efficient routing and avoiding voids during the molding process, which is achieved by rearranging the pad order and using a switch to re-route signals in different personalities of the SOC.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Ease of manufacture
If byte lanes are grouped together in traditional pad ordering, then routing within each byte lane is simplified, but routing congestion occurs in the corresponding half of the package when repackaging to smaller interfaces
Solution Approach 1:
The 64-bit DDR interface pads are segmented into two separate 32-bit interfaces by interleaving pads from different byte lanes. This segmentation allows the same physical interface to support both 64-bit and 32-bit configurations, eliminating routing congestion when repackaging to smaller interfaces while maintaining the manufacturing simplicity of grouped byte lanes through the interleaving pattern.
Solution Approach 2:
The patent introduces a new dimension to pad ordering by interleving pads from different byte lanes (e.g., byte lane 0, 2, 4, 6 in one sequence and byte lane 1, 3, 5, 7 in another) rather than keeping them contiguous. This dimensional reorganization of pad spatial arrangement distributes bond wires more evenly across the package, preventing routing congestion while maintaining byte lane integrity for routing purposes.
2Ease of manufacture
If only half of the interface pads are bonded out for repackaging, then package size is reduced, but voids are created in the unbonded areas causing wire sweep issues
Solution Approach 1:
The interface pads are segmented into two interleaved sets, where one set can be bonded out for 32-bit configurations while the other set remains unbonded. The interleaving pattern ensures that unbonded pads are distributed throughout the package rather than concentrated in one area, preventing large voids and associated wire sweep issues during molding while still achieving package size reduction.
Solution Approach 2:
The patent applies local quality by making different regions of the package have different bonding characteristics. Through interleaved pad ordering, some regions have bonded pads while adjacent regions have unbonded pads, creating a distributed pattern that maintains structural integrity and prevents wire sweep issues locally throughout the package during the molding process.
3Ease of manufacture
If multiple SOC personalities are derived from a single die, then design cost is reduced, but flexibility in physical interface layout is limited
Solution Approach 1:
The physical interface is designed with universal compatibility through interleaved pad ordering, allowing the same die to support multiple SOC personalities (64-bit DDR, 32-bit DDR, and other configurations) without requiring different physical layouts. The interleaved pattern enables flexible activation of different byte lane combinations, providing adaptability across multiple applications from a single die design.
Solution Approach 2:
The patent introduces dynamic reconfigurability to the physical interface through interleaved pad ordering, where the same physical pads can be dynamically assigned to different byte lane configurations depending on the SOC personality. This dynamic allocation allows flexible adaptation to different customer needs and application requirements while maintaining a single die design, thereby reducing costs while enhancing versatility.
Data Source
AI summary
A system on a chip (SOC) includes a physical interface having first and second sets of interface pads. Interface pads from the first set are interleaved with interface pads from the second set. Additionally, the SOC is arranged for operation with a superset die having first and second personalities and has a physical interface with interface pads. The SOC uses a first number of interface pads in the first personality and a second number of interface pads in the second personality, where the first number is greater than the second number. A switch switches signals between the superset die and the physical interface and, in the second personality, switches signals to the physical interface so that interface pads in the second number of interface pads are interleaved with interface pads not in use in the second personality.