Interleaved Storage Circuits for SIMD Data Access
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Solution Overview
Problem
In Single Instruction Multiple Data (SIMD) architectures, the latency of data processing elements is increased due to the need for multiple accesses to register banks when handling data elements, which consumes space and power, and existing methods require multiple accesses to the same storage circuit, leading to inefficiencies.
Innovation Solution
The implementation of a data processing device with storage circuits configured for interleaved storage of data elements, allowing a consumer to access either subsets of data elements or bits of each element in parallel, reducing the number of storage circuits and circuitry required, thereby minimizing latency and power consumption.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Productivity
If multiple register banks are provided to store data elements for parallel access, then data access parallelism is improved, but device complexity and power consumption increase
Solution Approach 1:
The patent segments data elements into multiple fields within each register bank, allowing different fields of different data elements to be stored in the same register bank. This segmentation enables parallel access to multiple data elements without requiring multiple separate register banks, thus improving productivity while controlling device complexity.
Solution Approach 2:
Each register bank is designed to be multi-functional by storing different fields of multiple data elements simultaneously. The register banks can serve multiple purposes: storing complete data elements, storing specific fields of data elements, and supporting both element-wise and field-wise access patterns, thereby reducing the total number of register banks needed.
2Adaptability or versatility
If multiple accesses to the same storage circuit are required, then data access flexibility is improved, but latency increases
Solution Approach 1:
The patent performs preliminary organization of data fields within register banks during the storage phase, arranging fields so that commonly accessed combinations are positioned for optimal parallel access. This preliminary arrangement ensures that subsequent access operations can retrieve required data in a single access cycle, preventing latency increases while maintaining flexibility.
Solution Approach 2:
The patent introduces a field dimension within each register bank, allowing access not only by data element index but also by field position. This additional dimension enables flexible data access patterns where specific fields of multiple data elements can be accessed simultaneously in parallel, maintaining versatility while avoiding multiple sequential accesses that would increase latency.
3Speed
If more storage circuits are used to reduce access latency, then data access speed is improved, but power consumption increases
Solution Approach 1:
The patent merges the storage of different fields of data elements into the same register bank, combining multiple storage functions into a single circuit. This merging reduces the total number of storage circuits required while maintaining the ability to access multiple data elements in parallel, thus improving data access speed without proportionally increasing power consumption.
Solution Approach 2:
The patent applies local quality optimization by allowing different register banks to store different field configurations optimized for specific access patterns. Each register bank can be locally optimized to store fields that are frequently accessed together, improving access speed for common operations while minimizing the number of active storage circuits and reducing overall power consumption.
Data Source
AI summary
A data processing device 100 comprises a plurality of storage circuits 130, 160, which store a plurality of data elements of the bits in an interleaved manner. Data processing device also comprises a consumer 110 with a number of lanes 120. The consumer is able to individually access each of the plurality of storage circuits 130, 160 in order to receive into the lanes 120 either a subset of the plurality of data elements or y bits of each of the plurality of data elements. The consumer 110 is also able to execute a common instruction of each of the plurality of lanes 120. The relationship of the bits is such that b is greater than y and is an integer multiple of y. Each of the plurality of storage circuits 130, 160 stores at most y bits of each of the data elements. Furthermore, each of the storage circuits 130, 160 stores at most y/b of the plurality of data elements. By carrying out the interleaving in this manner, the plurality of storage circuits 130, 160 comprise no more than b/y storage circuits.