Interleaved Via Bar Capacitors for Higher Capacitance Density
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Solution Overview
Problem
Existing capacitor structures in semiconductor devices face challenges in enhancing capacitance density without requiring additional manufacturing processes.
Innovation Solution
Incorporating via bars with a smaller width dimension than the capacitor plates, interleaved between the conductive plates, which are located at a half-pitch spacing, to enhance capacitance density.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Quantity of substance
If capacitor plates are made larger to increase capacitance, then capacitance increases, but device area increases
Solution Approach 1:
The patent transitions from planar capacitor plates to three-dimensional interleaved structures with via bars extending vertically between plates. This dimensional change allows capacitance to increase through vertical stacking and interleaving rather than horizontal expansion, effectively adding a Z-dimension to the capacitor geometry to boost capacitance density without increasing footprint area
Solution Approach 2:
The via bars are nested within the vertical space between capacitor plates, with multiple via bars positioned at different horizontal locations between the same pair of plates. This nesting approach allows multiple capacitive elements to occupy the same vertical column space, increasing total capacitance without requiring additional lateral area
2Quantity of substance
If via bars are added to increase capacitance density, then capacitance density increases, but manufacturing complexity increases
Solution Approach 1:
The via bars and capacitor plates are formed as integrated structures using the same deposition and patterning sequences. The via bar conductive material is deposited concurrently with or immediately adjacent to the capacitor plate material in unified process modules, merging what could be separate fabrication operations into combined steps that reduce overall manufacturing complexity
Solution Approach 2:
The via bar structures are prepared in advance as trenches or patterns in the dielectric material before final conductive material deposition. This preliminary structuring of the via bar locations and dimensions allows subsequent filling and planarization steps to proceed efficiently without requiring complex real-time adjustments during capacitor formation
Data Source
Figure 1A~1B
Figure 2
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AI summary
The present disclosure relates to semiconductor structures and, more particularly, to via bars interleaved between conductive plates of a capacitor structure and methods of manufacture. The structure includes: a capacitor structure having a plurality of capacitor plates within layers of dielectric material; a wiring structure in a lower layer of the dielectric material, the wiring structure electrically connecting to one of the capacitor plates; and a plurality of via bars within the layers of dielectric material and interleaved with the plurality of capacitor plates. The plurality of via bars have a different width dimension than the plurality of capacitor plates.