Interleaver Parameter Generation Without Large Address Tables
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Solution Overview
Problem
Existing interleaver designs for communication systems, particularly in wireless communication, require large amounts of processing power, circuit space, and introduce significant delay due to the need for pre-populating memory with MOD operation results for various block lengths, which is inefficient and power-hungry.
Innovation Solution
A hardware circuit that calculates interleaver parameters on an as-needed basis using a decomposed form of their definitions, eliminating the need for separate DSPs and large memory tables, thereby generating interleaver addresses efficiently without pre-calculating for all possible block lengths.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Speed
If pre-calculated address locations for all possible block lengths are stored in ROM or RAM, then interleaver addresses can be retrieved quickly, but large amounts of circuit space and processing power are required
Solution Approach 1:
The patent pre-calculates and stores only the necessary parameters (p, v, R, C, PRUNVAL) in lookup tables during design time, rather than storing complete address sequences. This preliminary preparation enables fast runtime operation without requiring large memory structures to hold all possible address patterns.
Solution Approach 2:
The patent extracts only the essential parameters needed to generate interleaver addresses (prime number p, primitive root v, matrix dimensions R and C, and pruning value PRUNVAL) from the full address calculation process. By storing only these extracted parameters rather than complete address sequences, the circuit space requirement is dramatically reduced while maintaining retrieval speed.
2Manufacturing precision
If separate address patterns are created for each block length, then accurate interleaving is achieved, but device complexity increases
Solution Approach 1:
The patent changes the approach from storing different address patterns for each block length to storing parameter sets (p, v, R, C, PRUNVAL) that can generate the appropriate addresses. By varying these parameters based on block length K, the system achieves accurate interleaving for different block lengths without requiring separate complete address patterns, thus reducing device complexity.
Solution Approach 2:
The patent creates a universal address generation mechanism that works for all block lengths using the same hardware structure. The lookup tables store parameters that can be combined with any block length K to generate the appropriate interleaver addresses, making the system multi-functional rather than requiring separate dedicated circuits for each block length.
3Adaptability or versatility
If MOD operations are performed at runtime for each address calculation, then flexibility is maintained, but processing latency increases
Solution Approach 1:
The patent performs the complex MOD operations and parameter calculations in advance during design time, storing the results in lookup tables. At runtime, the system simply retrieves pre-computed parameters and combines them with the current block length, eliminating runtime MOD operations and significantly reducing processing latency while maintaining flexibility through parameter variation.
Solution Approach 2:
The patent makes the system dynamic by allowing the retrieved parameters to vary based on the input block length K. The lookup tables are indexed by K, enabling the system to adapt to different block lengths dynamically without performing complex calculations at runtime, thus maintaining both flexibility and low latency.
Data Source
AI summary
An interleaver parameter generator circuit used to calculate and generate on an as needed basis interleaver parameters for interleaving blocks of information of varying lengths in accordance with a pseudorandom pattern defined by the 3GPP standard. The interleaver parameter generator circuit calculates and generates the defined interleaver parameters based on an input parameter that represents the length of the block of information to be interleaved. At least one of the defined parameters is calculated and generated using a decomposed form of its definition. The interleaver parameter generator circuit uses well known circuit blocks such as multipliers, subtractors, Compare-and-Select circuits and other circuits to calculate and generate the defined parameters.